ISL35822 Datasheet, PDF (33/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

ISL35822
Table 37. XENPAK DOM WARNING FLAGS REGISTER (Continued)
MDIO REGISTER, ADDRESS = 1.41076:7 (1.A074:5’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION⁽¹⁾
1.41076.3
1.41076.2
LBC_High
1 = Warning Set
0’b
LBC_Low
0 = Warning Not Set
0’b
RO
Laser Bias Current High Warning
RO
Laser Bias Current Low Warning
1.41076.1
LOP_High
0’b
RO
Laser Output Power High Warning
1.41076.0
LOP_Low
0’b
RO
Laser Output Power Low Warning
1.41077.15:8
Reserved
00’h
1.41077.7
1.41077.6
ROP_High 1 = Warning Set
0’b
ROP_Low
0 = Warn. Not Set
0’b
RO
Receive Optical Power High Warning
RO
Receive Optical Power Low Warning
1.41077.5:0
Reserved
00’h
Note (1): These 1-byte register values are merely copied by the ISL35822 from the I²C address space on Power-up or RESET, or on any DOM read operation. If the ‘Indirect
DOM Enable’ bit (Register bit 1.C018’h.2 Table 51) is not set, a four-lane external DOM device is expected to determine the values for these registers, according
Section 11.3 in the XENPAK MSA Rev 3.0 specification. A single one-lane DOM device system will provide the values from the single DOM device here. If the
‘Indirect DOM Enable’ bit is set, the values from the “Representative” (as defined by Register bits 1.C018’h.1:0 in Table 51), lane DOM are entered here.
Table 38. XENPAK DOM OPERATION CONTROL AND STATUS REGISTER
MDIO REGISTER, ADDRESS = 1.41216 (1.A100’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
1.41216.15:4
Reserved
0000’h
1.41216.3:2
1.41216.1:0
DOM
Command
Status⁽¹⁾
DOM
Command
Type⁽¹⁾
Current Status of DOM 00’b
Command
NVR operation to be
performed
11’b⁽²⁾
RO 11 = Command failed
10 = Command in progress/Queued
01 = Command complete w success
00 = Idle
R/W 00 = Single DOM Read operation
01 = Periodic update, slowest rate⁽³⁾
10 = Periodic update, intermediate rate⁽³⁾
11 = Periodic update, fastest rate⁽³⁾
Note (1): User writes to these bits are not valid unless the Command Status is Idle. The Command Status will not return to Idle until being read after command
completion (either Succeed or Failed).
Note (2): At the end of a hardware RESETN or a register 1.0.15 RESET operation, if the XP_ENA pin is asserted, and the DOM control bits are set in 1.32890 (1.807A),
the ISL35822 will automatically begin a ‘Periodic update, fastest rate read’ operation.
Note (3): The rates of the periodic reads are determined by bits 4:3 of register 1.49176 (1.C018’h), see Table 51.
VENDOR-SPECIFIC PMA/PMD AND GPIO REGISTERS (1.C001’H TO 1.C01D’H)
Table 39. PMA CONTROL 2 REGISTER
MDIO REGISTER, ADDRESS = 1.49153 (1.C001’h)
BIT
1.49153.15
1.49153.14
1.49153.13
NAME
PMA DC_O_DIS
Test
Amplitude adjust
SETTING
1 = Disable, 0 = normal
0 = normal
DEFAULT
0’b⁽¹⁾
0’b^{(2) (1)}
1,0’h^{(1) (3)}
R/W
R/W
R/W
R/W
DESCRIPTION
PMA DC Offset Disable
User must keep at 0.
Optimizing Setting, TBD⁽⁴⁾
1.49153.12:11
1.49153.10:8
Reserved
PMA_LOS_TH
1.49153.7:0
Reserved
0’h = 160mV_p-p
1’h = 240mV_p-p
2’h = 200mV_p-p
3’h = 120mV_p-p
4’h = 80mV_p-p
else = 160mV_p-p
0’h
LX4: ⁽³⁾ 0’h,
CX4:
03’h⁽¹⁾
R/W
00’h
Set the threshold voltage for the Loss Of
Signal (LOS) detection circuit in
PMA/PMD. Nominal levels are listed for
each control value. Note that the
differential peak-to-peak value is twice that
listed.
Note (1): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): Internal test purposes only.
Note (3): Default values depend on setting of LX4/CX4 select LX4_MODE pin. LX4 value is shown first.
Note (4): Optimum value to meet output templates. Contact BitBlitz for recommended value.
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