ISL35822 Datasheet, PDF (43/75 Pages) Intersil Corporation – Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

ISL35822
Table 68. PCS PARALLEL NETWORK LOOP BACK CONTROL REGISTER
MDIO REGISTER ADDRESS = 3.49156 (3.C004’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
3.49156.15:4
3.49156.3
3.49156.2
3.49156.1
3.49156.0
Reserved
PLP_3
PLP_2
PLP_1
PLP_0
1 = enable PCS Parallel
Network loopback⁽²⁾
0 = disable
0’b⁽¹⁾
0’b⁽¹⁾
0’b⁽¹⁾
0’b⁽¹⁾
R/W
PCS Parallel Network Loop Back Enable for each
individual lane. When high, routes the CX4/LX4 Serial
input to the CX4/LX4 Serial output via the XGMII side
of the PCS.
Note (1): The default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): Equivalent to a loopback at the XGMII input side of the PHY XS.
Table 69. PCS RECEIVE PATH TEST AND STATUS FLAGS
MDIO REGISTER ADDRESS = 3.49159 (3.C007’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
3.49159.15:12
Test Flags
0’h
ROLH Special test use only
3.49159.11
3.49159.10
3.49159.9
EFIFO_3
EFIFO_2
EFIFO_1
1 = EFIFO error in Lane 0’b
0 = no EFIFO error in
Lane
0’b
0’b
ROLH
ROLH
PCS Elasticity FIFO Overflow/Underflow Error
Detection⁽¹⁾
3.49159.8
3.49159.7
3.49159.6
3.49159.5
EFIFO_0
Code_3
Code_2
Code_1
0’b
1 = 10b/8b Code error in 0’b
Lane
0 = no 10b/8b Code error ^0’b
0’b
ROLH
ROLH
ROLH
ROLH
PCS 10b/8b Decoder Code Violation Detection⁽¹⁾
3.49159.4
Code_0
0’b
ROLH
3.49159.3:0
Test Flags
0’h
ROLH Special test use only
Note (1): Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the
LASI register 1.9003’h (see Table 27)
BIT
3.49160.15:14
3.49160.13
3.49160.12:10
3.49160.9
3.49160.8:6
3.49160.5
3.49160.12:10
3.49160.1
3.49160.0
Table 70. PMA/PCS OUTPUT CONTROL & TEST FUNCTION REGISTER
MDIO REGISTER ADDRESS = 3.49160 (3.C008’h)
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
Reserved
10’b
R/W
Test Function, do not alter
ENA_3
Enable Lane 3 O/P
1’b
R/W
0 = disable (indep. of LX4_MODE)
Reserved
010’b
R/W
Test Function, do not alter
ENA_2
Enable Lane 2 O/P
1’b
R/W
0 = disable (indep. of LX4_MODE)
Reserved
010’b
R/W
Test Function, do not alter
ENA_1
Enable Lane 1 O/P
1’b
R/W
0 = disable (indep. of LX4_MODE)
Reserved
010’b
R/W
Test Function, do not alter
ENA_0
Enable Lane 0 O/P
1’b
R/W
0 = disable (indep. of LX4_MODE)
Reserved
0’b
R/W
Test Function, do not alter
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