ISL6364 Datasheet, PDF (42/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
Voltage-Regulator (VR) Design
Materials
The tolerance band calculation (TOB) worksheets for VR output
regulation and IMON have been developed using the Root-Sum-
Squared (RSS) method with 3 sigma distribution point of the
related components and parameters. Note that the “Electrical
Specifications” table beginning on page 8 specifies no less than
6 sigma distribution point, not suitable for RSS TOB calculation.
To support VR design and layout, Intersil also developed a set of
worksheets and evaluation boards, as listed in Tables 15 and 16,
respectively. Contact Intersil’s local office or field support for the
latest available information.
TABLE 15. AVAILABLE DESIGN ASSISTANCE MATERIALS
Item
Description
0 VR12 Design and Validation
1 VR12 Design Worksheet for Compensation and Component Selection
2 Transient Response Optimization Guidelines
3 VOUT and IMON TOB Calculator
4 SVID and PMBus Communication Tool
5 Resistor Register Calculator
6 Dynamic VID Compensation Calculator
7 VR12 Layout Design Guidelines
8 TCOMP and TM Selection Worksheet
9 Fine Tune OCP and Droop Worksheet
10 Evaluation Board Schematics in OrCAD Format and Layout in
Allegro Format
NOTE: For worksheets, please contact Intersil Application support
at www.intersil.com/design/.
TABLE 16. AVAILABLE VR12 EVALUATION BOARDS
# OF # OF INTEGRATED
EVALUATION BOARDS PHASES
DRIVERS
PACKAGE
TARGETED APPLICATIONS
PEAK
PEAK
I²C/PMBUS EFFICIENCY CURRENT
ISL6366/67EVAL1 6+1
-
7x7 60 Ld High-End Desktop and Server
Yes
93%, 1.2V@50A 190A
with Discrete Drivers and
+25A
MOSFETs
ISL6366/67EVAL2 6+1
-
7x7 60 Ld High-End Desktop and Server
Yes
93.5%,
190A
with DrMOS
1.2V@50A
+25A
ISL6364EVAL1
4+1
-
6x6 48 Ld
Desktop/Memory
88%, 1.2V@50A 120A
+35A
ISL6363EVAL1
4+1
2+1
7x7 60 Ld
Desktop
88%, 1.2V@50A 120A
+35A
ISL6353EVAL1
3+0
2
5x5 40 Ld
Memory
94%, 1.5V@25A 100A
42
FN6861.0
December 22, 2010