ISL6364 Datasheet, PDF (19/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
L/DCR OR ESL/R_SEN MATCHING
Assuming the compensator design is correct, Figure 11 shows the
expected load transient response waveforms if L/DCR or
ESL/R_SEN is matching the R-C time constant. When the load
current I_OUT has a square change, the output voltage V_OUT also
has a square response, except for the overshoot at load release.
However, there is always some PCB contact impedance of current
sensing components between the two current sensing points; it
hardly accounts into the L/DCR or ESL/R_SEN matching calculation.
Fine tuning the matching is necessarily done in the board level to
improve overall transient performance and system reliability.
If the R-C timing constant is too large or too small, V_C(s) will not
accurately represent real-time I_OUT(s) and will worsen the
transient response. Figure 12 shows the load transient response
when the R-C timing constant is too small. V_OUT will sag
excessively upon load insertion and may create a system failure
or early overcurrent trip. Figure 13 shows the transient response
when the R-C timing constant is too large. V_OUT is sluggish in
drooping to its final value. There will be excessive overshoot if
load insertion occurs during this time, which may potentially hurt
the CPU reliability.
IOUT
VOUT
FIGURE 11. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
IOUT
VOUT
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO SMALL
IOUT
VOUT
FIGURE 13. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO LARGE
Channel-Current Balance for VR0
The sensed current I_n from each active channel is summed
together and divided by the number of active channels. The
resulting average current I_AVG provides a measure of the total
load current. Channel current balance is achieved by comparing
the sensed current of each channel to the average current to
make an appropriate adjustment to the PWM duty cycle of each
channel with Intersil’s patented current-balance method.
Channel current balance is essential in achieving the thermal
advantage of multiphase operation. With good current balance,
the power loss is equally dissipated over multiple devices and a
greater area.
Voltage Regulation
The compensation network shown in Figure 14 assures that the
steady-state error in the output voltage is limited only to the error
in the reference voltage (DAC & OFFSET) and droop current
source, remote sense, and error amplifier.
The sensed average current I_DROOP is tied to FB internally and
will develop voltage drop across the resistor between FB and
V_OUT for droop control. This current can be disconnected from the
FB node by tying R_{FS_DRP} high to VCC for non-droop applications.
The output of the error amplifier, V_COMP, is compared to the
internal sawtooth waveforms to generate the PWM signals. The
PWM signals control the timing of the Intersil MOSFET drivers
and regulate the converter output to the specified reference
voltage.
The ISL6364 does not have a unity gain amplifier in between the
feedback path and error amplifier. For remote sensing, connect the
microprocessor sensing pins to the non-inverting input, FB, via the
feedback resistor (R_FB), and inverting input, RGND, of the error
amplifier. This configuration effectively removes the voltage error
encountered when measuring the output voltage relative to the local
controller ground reference point. VSEN should connect to remote
sensing’s positive rail as well for over voltage protection.
EXTERNAL CIRCUIT
R_C C_{C COMP}
ISL6364
I_DROOP
R_FB
+
V_DROOP
-
V_OUT
FB
RGND
VSEN
ERROR
AMPLIFIER
-
++
+
V_COMP
VID &
OFFSET
DAC
-
OVP
+-
+
FIGURE 14. OUTPUT VOLTAGE AND LOAD-LINE REGULATION
A digital-to-analog converter (DAC) generates a reference voltage,
which is programmable via SVID bus. The DAC decodes the SVID
set command into one of the discrete voltages shown in Table 4
on page 20. In addition, the output voltage can be margined in
±5mV step between -640mV and 635mV, as shown in Table 5 on
page 23, via SVID set OFFSET command (33h). For a finer than
5mV offset, a large ratio resistor divider can be placed on the FB
pin between the output and GND for positive offset or VCC for
negative offset.
VR1’s VSENS, RGNDS, FBS, and COMPS pins function in the
similar manner as VR0’s VSEN, RGND, FB, and COMP pins.
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FN6861.0
December 22, 2010