ISL6364 Datasheet, PDF (35/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
Disabling Output
When disabling any output, its respective pins should be tied
accordingly as in Table 13. However, when both outputs are fully
populated, pulling the respective PWM line to VCC should be
sufficient.
TABLE 13. DISABLE OUTPUT CONFIGURATION
DISABLE VR1 OUTPUT
PIN NAME
PIN CONFIGURATION
PWMS
VCC
RNGDS; VSENS;
GND
FBS; IMONS;
ISENS-; VR_RDYS
HFCOMPS/DVCS;
ISENS+
OPEN
FSS_DRPS
1MΩto GND (for 0,2,4,6 ADDR)
or 1MΩ to VCC for 8,A,C ADDR)
TMS
Connect To TM pin or a 1/2 ratio Resistor Divider
(1MΩ/2MΩ) to avoid tripping VR_HOT#; or Use it
as a second thermal sensing for VR_HOT#. DON’T
tie it to VCC or GND.
DISABLE VR0 OUTPUT
PIN NAME
PIN CONFIGURATION
PWM1
VCC
RNGD; VSEN;
GND
FB; IMON;
ISEN[1:4]-; VR_RDY
HFCOMP; ISEN[1:6]+
OPEN
FS_DRP, RSET
1MΩ to GND
TM
Connect To TMS pin or a 1/2 ratio Resistor Divider
(1MΩ/2MΩ) to avoid tripping VR_HOT#; or Use it
as a second thermal sensing for VR_HOT#. DON’T
tie it to VCC or GND.
SVID Operation
The device is fully compliant with Intel VR12/IMVP7 SVID protocol
Rev 1.5, document# of 456098. To ensure proper CPU operation,
refer to this document for SVID bus design and layout guidelines;
each platform requires different pull-up impedance on the SVID bus,
while impedance matching and spacing among DATA, CLK, and
ALERT# signals must be followed. Common mistakes are insufficient
spacing among signals and improper pull-up impedance. A simple
operational instruction of SVID bus with Intel VTT Tool is documented
in “VR12 Design and Validation” in Table 15.
General Design Guide
This design guide is intended to provide a high-level explanation of
the steps necessary to create a multiphase power converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following. In addition to this
guide, Intersil provides complete reference designs, which include
schematics, bills of materials, and example board layouts for
common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to determine
the number of phases. This determination depends heavily upon
the cost analysis, which in turn depends on system constraints
that differ from one design to the next. Principally, the designer
will be concerned with whether components can be mounted on
both sides of the circuit board; whether through-hole components
are permitted; and the total board space available for power
supply circuitry. Generally speaking, the most economical
solutions are those in which each phase handles between 15A
and 25A. All surface-mount designs will tend toward the lower
end of this current range. If through-hole MOSFETs and inductors
can be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 40A per phase, but these designs require heat
sinks and forced air to cool the MOSFETs, inductors and heat-
dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct; the switching frequency; the capability of
the MOSFETs to dissipate heat; and the availability and nature of
heat sinking and air flow.
Lower MOSFET Power Calculation
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower MOSFET is
due to current conducted through the channel resistance
(r_DS(ON)). In Equation 31, I_M is the maximum continuous output
current; I_PP is the peak-to-peak inductor current (see Equation 1
on page 14); d is the duty cycle (V_OUT/V_IN); and L is the per-
channel inductance.
P_{LOW, 1}
=
r_DS(ON)
⎛
⎜
I--_{M---⎟⎞}
⎝ N⎠
2
+
-I-^P----^P--²-
12
⋅ (1 – d)
(EQ. 31)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the lower-MOSFET
body diode. This term is dependent on the diode forward voltage
at I_M, V_D(ON); the switching frequency, F_sw; and the length of
dead times, t_d1 and t_d2, at the beginning and the end of the
lower-MOSFET conduction interval respectively.
P_{LOW, 2}
=
V_D(ON) F_SW
⎛
⎝
-I-^M---
N
+
I--_{P--2--P--⎠⎞}
t_d1
+
⎛
⎜
I--_M---
⎝N
–
-I-^P----^P--⎟⎞
2⎠
t_d2
(EQ. 32)
Finally, the power loss of output capacitance of the lower
MOSFET is approximated in Equation 33:
P_L
O W ,3
≈
2_--
3
⋅
V_I1N.5
⋅
C _{O S S _LOW}
⋅
V_{DS_LOW} ⋅ F_SW
(EQ. 33)
where C_{OSS_LOW} is the output capacitance of the lower MOSFET at
the test voltage of V_{DS_LOW}. Depending on the amount of ringing,
the actual power dissipation will be slightly higher than this.
Thus the total maximum power dissipated in each lower MOSFET is
approximated by the summation of P_LOW,1, P_LOW,2 and P_LOW,3.
Upper MOSFET Power Calculation
In addition to r_DS(ON) losses, a large portion of the upper-MOSFET
losses are due to currents conducted across the input voltage (V_IN)
during switching. Since a substantially higher portion of the
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FN6861.0
December 22, 2010