ISL6364 Datasheet, PDF (14/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
as illustrated in Figure 1. The three channel currents (IL1, IL2,
and IL3) combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM pulse is
terminated 1/3 of a cycle after the PWM pulse of the previous
phase. The DC components of the inductor currents combine to
feed the load.
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine Equation 1, which represents an
individual channel’s peak-to-peak inductor current.
I_{PP =}
(_{---V----I--N-----}–_{-----V----O-----U----T---})_----⋅_{----V----O----U-----T-}
L ⋅ F_SW ⋅ V_IN
(EQ. 1)
In Equation 1, V_IN and V_OUT are the input and output voltages
respectively, L is the single-channel inductor value, and F_SW is
the switching frequency.
IL1 + IL2 + IL3, 7A/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
IL2, 7A/DIV
IL3, 7A/DIV
PWM2, 5V/DIV
PWM3, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR
3-PHASE CONVERTER
In the case of multiphase converters, the capacitor current is the
sum of the ripple currents from each of the individual channels.
Compare Equation 1 to the expression for the peak-to-peak
current after the summation of N symmetrically phase-shifted
inductor currents in Equation 2, the peak-to-peak overall ripple
current (I_C,PP) decreases with the increase in the number of
channels, as shown in Figure 2.
N=1
2
3
4
5
6
DUTY CYCLE (V_OUT/V_IN)
FIGURE 2. RIPPLE CURRENT MULTIPLIER vs DUTY CYCLE
Output voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and the summed inductor
ripple current. Increased ripple frequency and lower ripple
amplitude mean that the designer can use less per-channel
inductance and few or less costly output capacitors for any
performance specification.
I_{C, PP}=
---^V----^O---^U----^T----
L ⋅ F_SW
K_R
C
M
K_RCM = -⁽--^N-----^â‹---^D------–----^m-------+----_N-¹----⁾-_â‹--^â‹-_D--⁽---^m-------–----⁽--^N------^â‹---^D----⁾---⁾
(EQ. 2)
for
m–1≤N⋅D≤m
m = ROUNDUP(N ⋅ D, 0)
Another benefit of interleaving is to reduce input ripple current.
Input capacitance is determined in part by the maximum input
ripple current. Multiphase topologies can improve overall system
cost and size by lowering input ripple current and allowing the
designer to reduce the cost of input capacitors. The example in
Figure 3 illustrates input currents from a three-phase converter
combining to reduce the total input ripple current.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DI
FIGURE 3. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR
RMS CURRENT FOR 3-PHASE CONVERTER
The converter depicted in Figure 3 delivers 36A to a 1.5V load from
a 12V input. The RMS input capacitor current is 5.9A. Compare this
to a single-phase converter also stepping down 12V to 1.5V at 36A.
The single-phase converter has 11.9A_RMS input capacitor current.
The single-phase converter must use an input capacitor bank with
twice the RMS current capacity as the equivalent three-phase
converter.
Figures 29, 30 and 31, as described in “Input Capacitor
Selection” on page 38 , can be used to determine the input
capacitor RMS current based on load current, duty cycle, and the
number of channels. They are provided as aids in determining
the optimal input capacitor solution. Figure 32 shows the single
phase input-capacitor RMS current for comparison.
PWM Modulation Scheme
The ISL6364 adopts Intersil's proprietary Enhanced Active Pulse
Positioning (EAPP) modulation scheme to improve transient
performance. The EAPP is a unique dual-edge PWM modulation
scheme with both PWM leading and trailing edges being
14
FN6861.0
December 22, 2010