ISL6364 Datasheet, PDF (39/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
0.6
0.4
0.2
I_L,PP = 0
I_L,PP = 0.5 I_O
I_L,PP = 0.75 I_O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_OUT/V_IN)
FIGURE 32. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR SINGLE-PHASE CONVERTER
MULTIPHASE RMS IMPROVEMENT
Figure 32 is provided as a reference to demonstrate the dramatic
reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a 2-phase
converter versus that of a single phase. Assume both converters
have a duty cycle of 0.25, maximum sustained output current of
40A, and a ratio of I_L,PP to I_O of 0.5. The single phase converter
would require 17.3A_RMS current capacity while the 2-phase
converter would only require 10.9A_RMS. The advantages become
even more pronounced when output current is increased and
additional phases are added to keep the component cost down
relative to the single phase approach.
Layout and Design Considerations
The following layout and design strategies are intended to minimize
the noise coupling, the impact of board parasitic impedances on
converter performance and to optimize the heat-dissipating
capabilities of the printed-circuit board. These sections highlight
some important practices which should follow during the layout
process. A layout check list in excel format is available for use.
Pin Noise Sensitivity, Design and Layout
Consideration
Table 14 below shows the noise sensitivity of each pin and their
design and layout consideration. All pins and external
components should not be across switching nodes and placed in
general proximity to the controller.
TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION
PIN NAME
EN_PWR
NOISE
SENSITIVITY
DESCRIPTION
No
There is an internal 1µs filter. Decoupling
capacitor is NOT needed, but if needed,
use a low time constant one to avoid too
much of shut-down delay. It will also be the
output of OVP function in ISL6364A: 34Ω
strong pull-up. 25 mils spacing from other
traces.
TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION
(Continued)
NOISE
PIN NAME SENSITIVITY
DESCRIPTION
RAMP_ADJ
Yes NO decoupling capacitor allowed on this
pin, but decoupling its resistor pull-up RAIL
with a high quality ceramic capacitor
(0.1µF or higher) or with very small RC
filter (<2.2µs).
RGND
Yes Pairing up with the positive rail remote
sensing line that connected to FB resistor,
and routing them to the load sensing
points.
VSEN
No
Used for Overvoltage protection sensing
only, and it has 1µs internal filter.
Decoupling is NOT needed. Add a ZERO
Ohm series impedance to be compatible
with ISL6364A.
FB
Yes
Pairing up with the negative rail of remote
sensing line that connected to RGND, and
routing them to the load sensing points.
Reserve an RC from FB to GND to
compensate the output lagging from DAC
during DVID transitions.
HFCOMP
Yes Connect an R to the VR0 output. The R
value is typically equal or slightly higher
than the feedback resistor (droop resistor),
fine tuned according to the high frequency
transient performance. Placing the
compensation network in close proximity
to the controller.
PSICOMP
Yes The series impedance typically should be
2x-3x the impedance in type III
compensation to reduce noise coupling.
Placing the compensation network in close
proximity to the controller.
COMP
Yes
Placing the compensation network in close
proximity to the controller. Typically use a
68pF or higher across FB to COMP
depending upon the noise coupling of the
layout.
IMON
Yes Referring to GND, not RGND. Place R and C
in general proximity to the controller. The
time constant of RC should be sufficient,
typically 1ms, as an average function for
the digital IOUT of VR0.
SVDATA;
SVCLK
Yes 13 to 26MHz signals when the SVID bus is
sending commands, pairing up with
SVALERT# and routing carefully back to
CPU socket. 20 mils spacing within
SVDATA, SVALERT#, and SVCLK; and more
than 30 mils to all other signals. Refer to
the Intel individual platform design
guidelines and place proper terminated
(pull-up) resistance for impedance
matching. Local decoupling capacitor is
needed for the pull-up rail.
SVALERT#
No
Open drain and high dv/dt pin during
transitions. Routing it in the middle of
SVDATA and SVCLK. Also see above.
39
FN6861.0
December 22, 2010