ISL6364 Datasheet, PDF (34/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
TABLE 12. TIE-HIGH AND TIE-LOW OPTIONS (Continued)
REG
0C
ADDR
IMAXS
(R_{FSS_DRPS}:
GND/VCC)
TMAX
R_UP R_DW DATA
6/7
20A/15A
95°C OPEN 499kΩ DFh
BTS
(R_{FSS_DRPS}:
0D GND/VCC)
DES
TCOMPS
1.1V/1.5V DISABLED +29.7°C OPEN 10kΩ 00h
1.1V/1.5V ENABLED +29.7°C 10kΩ OPEN 1Fh
0
DISABLED +29.7°C OPEN 499kΩ C0h
0
ENABLED +29.7°C 499kΩ OPEN DFh
BT (R_{FS_DRP}:
0E GND/VCC)
FDVID
TCOMP
1.1V/1.05V 10mV/µs +29.7°C OPEN 10kΩ 00h
1.1V/1.05V 20mV/µs +29.7°C 10kΩ OPEN 1Fh
0
10mV/µs +29.7°C OPEN 499kΩ C0h
0
20mV/µs +29.7°C 499kΩ OPEN DFh
0F
NPSI
DE
IMAX
SI1/CI1
ENABLED
100A OPEN 10kΩ 00h
SI1/CI1
ENABLED
165A 10kΩ OPEN 1Fh
SI2/CI2 DISABLED 100A OPEN 499kΩ C0h
SI2/CI2 DISABLED 165A 499kΩ OPEN DFh
NOTE: Whenever 10kΩ is tie-high or tie-low, 0Ω can be used.
Dynamic VID Compensation (DVC)
During a VID transition, the resulting change in voltage on the FBS
pin and the COMPS pin causes an AC current to flow through the
error amplifier compensation components from the FBS to the
COMPS pin. This current then flows through the feedback resistor,
R_FBS, and can cause the output voltage to overshoot or undershoot
at the end of the VID transition. In order to ensure the smooth
transition of the output voltage during a VID change, a VID-on-the-fly
compensation network is required. This network is composed of a
resistor and capacitor in series, R_DVC and C_DVC, between the DVCS
and the FBS pin.
This VID-on-the-fly compensation network works by sourcing AC
current into the FBS node to offset the effects of the AC current
flowing from the FBS to the COMPS pin during a VID transition. To
create this compensation current, the controllers set the voltage
on the DVCS pin to be 4/3 of the voltage on the DAC. Since the
error amplifier forces the voltage on the FBS pin and the DAC to
be equal, the resulting voltage across the series RC between
DVCS and FBS is equal to the DAC voltage. The RC compensation
components, R_DVC and C_DVC, can then be selected to create the
desired amount of compensation current.
VOUT
DVCS
R_FBS ^IDVC ^{= I}C
C ^IRC R
C_DVC ^IDVC R_DVC
I_C
C_C
FBS
R_C
COMPS
x1.333
-
+ _ERROR
AMPLIFIER
V_DAC
I_RC+I_{DROOP_ACTUAL}
ISL6364 INTERNAL CIRCUIT
FIGURE 28. DYNAMIC VID COMPENSATION NETWORK
The amount of compensation current required is dependant on
the modulator gain of the system, K1, and the error amplifier R-C
components, R_C and C_C, that are in series between the FBS and
COMPS pins. Use Equations 26, 27, and 28 to calculate the RC
component values, R_DVC and C_DVC, for the VID-on-the-fly
compensation network. For these equations: V_IN is the input
voltage for the power train; V_RAMP is the oscillator ramp
amplitude as in Equation 3; and R_C and C_C are the error amplifier
R-C components between the FBS and COMPS pins.
K1 = -----^V----^I--^N------
V_RAMP
(EQ. 26)
R_DVC = A ⋅ R_C
A
=
------------^K----¹-------------
3 ⋅ (K1 – 1)
(EQ. 27)
C_DVC
=
-^C---^C--
A
(EQ. 28)
During DVID transitions, extra current builds up in the output
capacitors due to the C*dv/dt. The current is sensed by the
controller and fed across the feedback resistor creating extra
droop (if Enabled) and causing the output voltage not properly
tracking the DAC voltage. Placing a series R-C to ground from the
FB pin can sink this extra DVID induced current.
C
=
C_{----O----U----T----}⋅_---R_----L---L-
R_FBS
(EQ. 29)
R
=
-^C---^O----^U----^T----^â‹---^R----^L---^L-
C
=
R_FBS
(EQ. 30)
When the output voltage overshoots during DVID, the RDVC-CDVC
network can be used to compensate the movement of the
error-amplifier compensation network. When the output voltage
is lagging from DAC (or SVALERT#) or having a rough-off prior to
the final settling of DVID, the R-C network can be used to
compensate for the extra droop current generated by the
C*dv/dt. Sometimes, both networks can work together to
achieve the best result. In such case, both networks need to be
fine tuned in the board level for optimized performance.
Only VR1 is available for DVC compensation when the droop is
disabled, while the R-C network to compensate the lagging of
VOUT from DAC is applicable for both VR1 and VR0 when needed.
34
FN6861.0
December 22, 2010