ISL6364 Datasheet, PDF (13/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
IMAXS - An input pin to set the maximum current, I_CCMAX,
register of the VR1. It can be programed to 20A, 25A, 30A, and
35A when the droop is enabled (R_{FSS_DRPS} = GND). This register
represents the maximum allowed load current for VR1 and
corresponds to a 900mV (typically set) at IMONS. When VR1
droop is disabled (R_{FSS_DRPS} = VCC), the I_CCMAX can be
programed to15A, 20A, 25A, and 30A.
TMAX - An input pin to set the maximum temperature register
(TMAX) of the VR0 and VR1 and the thermal trip point of
VR_HOT#. It covers +90°C to +120°C with 5°C/step. The
register represents the maximum allowed temperature of VR0
and VR1, and programs the over-temperature trip point at
VR_HOT#. The typical application should use +100°C or lower
since the NTC thermistor temperature represents the PCB, not
the hottest component on the board. In addition, the NTC
thermistor typically picks up a temperature lower than the PCB
due to the thermal impedance between PCB and NTC.
BTS_DES_TCOMPS (0D):
BTS - An input pin to set the start-up boot voltage register of VR1.
It has four levels: 0, 0.9V, 1.0, and 1.1V for graphic rails with
droop enabled (R_{FSS_DRPS} = GND). When the droop is disabled
(R_{FSS_DRPS} = VCC), the boot levels will be changed to 0, 0.85V,
0.925V, 1.05V for VCCIO and System Agent rails.
DES - An input pin to set the diode emulation (DE) operation
register of VR1 at PSI2, PSI3, and Decay modes. At PSI1 mode,
the VR1 always operates in CCM mode. When the diode
emulation is disabled, the output will decay at the rate of setVID
Slow; however, the SVID bus is still be acknowledged of execution
of the command.
TCOMPS - An input pin to set the mis-matching temperature
(+13°C to +43°C) between the actual sensed inductor and the NTC
thermistor at TMS pin. The voltage sensed on the TMS pin is utilized
as the temperature input to adjust the droop current and the
overcurrent protection limit to effectively compensate for the
temperature coefficient of the current sense element of VR1. To
implement the integrated temperature compensation, select a
proper temperature offset “TCOMP,” other than the “OFF” value,
which is to disable the integrated temperature compensation
function.
BT_FDVID_TCOMP (0E):
BT - An input pin to set the start-up boot voltage register of VR0.
It has four levels: 0V, 0.9V, 1.0V, and 1.1V for core applications
with droop enabled (R_{FS_DRP} = GND). When the droop is
disabled (R_{FS_DRP} = VCC), the boot levels will be changed to 0V,
1.2V, 1.35V, and 1.5V for memory applications.
FDVID - An input pin to set the slew rate of fast Dynamic VID. It
has choices of 10mV/µs and 20mV/µs. This will only apply to
VR0, not VR1.
TCOMP - An input to set the mis-matching temperature (+13°C to
+43°C) between the actual sensed inductor of VR0 regulator and
the NTC thermistor at the TM pin. The voltage sensed on the TM pin
is utilized as the temperature input to adjust the droop current and
the overcurrent protection limit to effectively compensate for the
temperature coefficient of the current sense element of VR0. To
implement the integrated temperature compensation, select a
proper temperature offset “TCOMP,” other than the “OFF” value,
which is to disable the integrated temperature compensation
function.
NSPI_DE_IMAX (0F):
NPSI - An input pin to set the number of phases dropping at low
power mode. See Table 3 on page 16 for more details.
DE - An input pin to set the diode emulation (DE) operation
register of VR0 at PSI2, PSI3, and Decay modes. At PSI1 mode,
the VR0 always operates in CCM mode. When the diode
emulation is disabled, the output will decay at the rate of setVID
Slow; however, the SVID bus is still be acknowledged of execution
of the command.
IMAX - An input pin to set the maximum current, I_CCMAX, register
of the VR0 voltage regulator. It has a range of 15A to 165A with
5A/step.This register represents the maximum allowed load
current for VR0 and corresponds to a 900mV (typically set) at
IMON.
Operation
The ISL6364 is a dual PWM controller; its 4-phase PWMs control
microprocessor core or memory voltage regulator, while its single-
phase PWM controls the peripheral voltage regulator such
graphics rail, system agent, or processor I/O. The ISL6364 is
designed to be compliant to Intel VR12/IMVP7 specifications with
SerialVID Features. The system parameters and SVID required
registers are programmable with four dedicated pins. It greatly
simplifies the system design for various platforms and lowers
inventory complexity and cost by using a single device.
In addition, this controller is compatible, except for forced phase
dropping via PWM lines, with phase doublers (ISL6611A and
ISL6617), which can double or quadruple the phase count. For
instance, the multi-phase PWM can realize a beyond 4-phase and
up to 16-phase count system, and the single-phase PWM can be
scaled up to 2 or 4 phases. The higher phase count system can
improve thermal distribution and power conversion efficiency at
heavy load.
Multiphase Power Conversion
Microprocessor load current profiles have changed to the point
that the advantages of multiphase power conversion are
impossible to ignore. The technical challenges associated with
producing a single-phase converter (which are both cost-effective
and thermally viable), have forced a change to the cost-saving
approach of multiphase. The ISL6364 controller helps reduce the
complexity of implementation by integrating vital functions and
requiring minimal output components. The typical application
circuits diagrams on page 5 and page 6 provide the top level
views of multiphase power conversion using the ISL6364
controller.
Interleaving
The switching of each channel in a multiphase converter is timed
to be symmetrically out-of-phase with each of the other channels.
In a 3-phase converter, each channel switches 1/3 cycle after the
previous channel and 1/3 cycle before the following channel. As
a result, the 3-phase converter has a combined ripple frequency
three times greater than the ripple frequency of any one phase,
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FN6861.0
December 22, 2010