ISL6364 Datasheet, PDF (41/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION
(Continued)
NOISE
PIN NAME SENSITIVITY
DESCRIPTION
FS_DRP
Yes
Placing the R in close proximity to the
controller. Must tie GND or VCC via 1MΩ
when VR0 is not in use. Don’t use
decoupling capacitor on this pin.
VCC
Yes
Place the decoupling capacitor in close
proximity to the controller.
PWM1-4
NO
Avoid the respective PWM routing across
or under other phase’s power
trains/planes and current sensing
network. Don’t make them across or under
external components of the controller. At
least 20mils away from any other traces.
EN_VTT
No
There is an internal 1µs filter. Decoupling
capacitor is not needed, but if needed, use
a low timing constant one to avoid too
much shut-down delay.
ISEN[4:1]+
Yes
Connect to the output rail side of the
respective channel’s output inductor or
resistor pin. Decoupling is optional and
might be required for long sense traces
and a poor layout.
ISEN[4:1]-
Yes
Connect to the phase node side of the
respective channel’s output inductor or
resistor pin with L/DCR or ESL/R_SEN
matching network in close proximity to the
ISEN± pins of VR0. Differentially routing
back to the controller by paring with
respective ISEN+; at least 20 mils spacing
between pairs and away from other traces.
Each pair should not across or under the
other channel’s switching nodes [Phase,
UGATE, LGATE] and power planes even
though they are not in the same layer.
GND
Yes
This EPAD is the return of PWM output
drivers and SVID bus. Use 4 or more vias to
directly connect the EPAD to the power
ground plane. Avoid using only single via or
0Ω resistor connection to the power
ground plane.
General
Comments
The layer next to the Top or Bottom layer is
preferred to be ground players, while the
signal layers can be sandwiched in the
ground layers if possible.
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most critical
because they carry large amounts of energy and tend to generate
high levels of noise. Switching component placement should take
into account power dissipation. Align the output inductors and
MOSFETs such that space between the components is minimized
while creating the PHASE plane. Place the Intersil MOSFET driver
IC as close as possible to the MOSFETs they control to reduce the
parasitic impedances due to trace length between critical driver
input and output signals. If possible, duplicate the same
placement of these components for each phase.
Next, place the input and output capacitors. Position the high-
frequency ceramic input capacitors next to each upper MOSFET
drain. Place the bulk input capacitors as close to the upper
MOSFET drains as dictated by the component size and
dimensions. Long distances between input capacitors and
MOSFET drains result in too much trace inductance and a
reduction in capacitor performance. Locate the output capacitors
between the inductors and the load, while keeping them in close
proximity to the microprocessor socket.
To improve the chance of first pass success, it is very important
to take time to follow the above outlined design guidelines and
Intersil generated layout check list, see more details in “Voltage-
Regulator (VR) Design Materials” on page 42. Proper planning for
the layout is as important as designing the circuits. Running
things in a hurry, you could be end up spending weeks and
months to debug a poorly-designed and improper-layout board.
Powering Up And Open-Loop Test
The ISL6364 features very easy debugging and powering up. For
the first-time powering up, an open-loop test can be done by
applying sufficient voltage (current limiting to 0.25A) to VCC,
proper pull-up to SVID bus, and signal high to EN_VTT and
EN_PWR pins with the input voltage (VIN) disconnected.
1. Each PWM output should operate at maximum duty cycle
(typically VR0 at 98% and VR1 at 83%) and correct switching
frequency.
2. The 0C, 0D, 0E, and 0F registers can be read via SVID bus to
check its proper setting if an VTT tool is installed and
operating.
3. If 5V drivers are used and share the same rail as VCC, the
proper switching on UGATEs and LGATEs should be seen.
4. If 12V drivers are used and can be disconnected from VIN and
sourced by an external 12V supply, the proper switching on
UGATEs and LGATEs should be observed.
5. If the above is not properly operating, you should check
soldering joint, resistor register setting, Power Train
connection or damage, i.e, shorted gates, drain and source.
Sometimes the gate might be measured short due to residual
gate charge. Therefore, a measured short gate with
ohmmeter cannot validate if the MOSFET is damaged unless
the Drain to Source is also measured short.
6. When the re-work is needed for the L/DCR matching network,
use an ohmmeter across the C to see if the correct R value is
measured before powering the VR up; otherwise, the current
imbalance due to improper re-work could damage the power
trains.
7. After everything is checked, apply low input voltage (1-5V)
with appropriate current limiting (~0.5A). All phases should
be switching evenly.
8. Remove the pull-up from EN_PWR pin, using bench power
supplies, power up VCC with current limiting (typically ~ 0.25A
if 5V drivers included) and slowly increase Input Voltage with
current limiting. For typical application, VCC limited to 0.25A,
VIN limited to 0.5A should be safe for powering up without no
load. High core-loss inductors likely need to increase the input
current limiting. All phases should be switching evenly.
41
FN6861.0
December 22, 2010