ISL6364 Datasheet, PDF (15/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
independently moved to give the best response to transient
loads. The EAPP has an inherited function, similar to Intersil's
proprietary Adaptive Phase Alignment (APA) technique, which
turns on all phases together in order to further improve the
transient response when there are sufficiently large load step
currents. The EAPP is a variable frequency but linear control over
the transient events such that it can evenly distribute the pulses
among all phases to achieve a very good current balance and
eliminate the beat frequency oscillation over wide frequency
range of load transients.
To further improve the line and load transient responses, the
multi-phase PWM features feedforward function to change the
up ramp with the input line to maintain a constant overall loop
gain over a wide range input voltage. The up ramp of the internal
Sawtooth is defined in Equation 3.
V_RAMP
=
------⁵------^â‹--¹----⁰----¹---⁰----^â‹----^V---^I--^N-------
F_SW
⋅
R
RA
M
P _ADJ
(EQ. 3)
With EAPP control and feedforward function, the ISL6364 can
achieve excellent transient performance over wide frequency
range of load step, resulting in lower demand on the output
capacitors.
At DC load conditions, the PWM frequency is constant and set by
the external resistor between the FS pin and GND during normal
mode (PSI0) and low power mode (PSI1). However, when PSI2 or
PSI3 is asserted in ultra low power conditions and if the VR is
configured into diode emulation operation, the EAPP reduces the
switching frequency as the load decreases. Thus, the VR can
enter burst mode at extreme light load conditions and improve
power conversion efficiency significantly.
Under steady state conditions, the operation of the ISL6364
PWM modulator appears to be that of a conventional trailing
edge modulator. Conventional analysis and design methods can
therefore be used for steady state and small signal operation.
The single-phase PWM has a fix ramp of 2V peak to peak. Its
modulation gain does not change with the input line.
PWM and PSI# Operation
The timing of each channel is set by the number of active
channels. The default channel setting for the ISL6364 is four. The
switching cycle is defined as the time between PWM pulse
termination signals of each channel. The cycle time of the pulse
signal is the inverse of the switching frequency set by the resistor
between the FS pin and ground. The PWM signals command the
MOSFET driver to turn on/off the channel MOSFETs.
The ISL6364 can work in a 0 to 4-Phase configuration. Tie
PWM(N+1) to VCC to configure for N-phase operation. PWM firing
order is sequential from 1 to N with N being the number of active
phases, as summarized in Table 1. For 4-phase operation, the
channel firing sequence is 1-2-3-4, and they are evenly spaced
1/4 of a cycle. Connecting PWM4 to VCC configures 3-phase
operation, the channel firing order is 1-2-3 and the phase spacing
is 1/3 of a cycle. If PWM2 is connected to VCC, only Channel 1
operation is selected. If PWM1 is connected to VCC, the
multi-phase (VR0) operation is turned off; to ensure proper
operation of VR1, the VR0’s respective pins should be configured
as described in “Disabling Output” on page 35.
TABLE 1. PHASE NUMBER AND PWM FIRING SEQUENCE
PHASE SEQUENCE
N
PSI# = PSI0
PWM# TIED
TO VCC
ACTIVE PHASE
PSI# = PSI1
4
1-2-3-4
-
PWM1/3
3
1-2-3
PWM4
PWM1/2
2
1-2
PWM3
PWM1/2
1
1
PWM2
PWM1
0
OFF
PWM1
OFF
The CPU can enter four distinct power states, as shown in Table 2.
The ISL6364 supports all states, but it treats PSI2 and PSI3 the
same. In addition, the setDecay mode will automatically enter PSI2
state while decaying the output voltage. However, prior to the end of
soft-start (i.e: VR_RDY goes high), the lower power mode
(PSI1/2/3/Decay) is NOT enabled.
TABLE 2. POWER STATE COMMAND FROM CPU
STATE
DESCRIPTION
PSI0 High Power Mode, All Phases are running
PSI1 Low Power Mode
PSI2 Very Low Power Mode
PSI3 Ultra Low Power Mode, treated as PSI2
Decay Automatically entering PSI2 and Ramping down the output
voltage to a target voltage in Decay Mode
When the SVID bus sends PSI1/2/3 or setVID Decay command, it
indicates the low power mode operation of the processor. The
controller will start phase shedding the next switching pulse. The
controller allows to drop the number of active phases according to
the logic on Table 3 for high light load efficiency performance. The
“NPSI” register and SICI pin are to program the controller in
operation of non-coupled (SI), 2-phase coupled, or (N-x)-Phase
coupled inductors. Different cases yield different PWM output
behaviors on both dropped phase(s) and operational phase(s) as
PSI# is asserted and de-asserted. When CPU sends PSI0 command,
it will pull the controller back to normal CCM PWM operation to
sustain an immediate heavy transient load and high efficiency. Note
that “N-x” means N-x phase coupled and x phase(s) are uncoupled.
For 2-Phase coupled inductor (CI) operation, both coupled phases
should be 180° out of phase. In low power states
(PSI1/2/3/Decay), the opposite phase of the operational phase
will turn on its Low-side MOSFET to circulate inductor current to
minimize conduction loss when Phase 1 is high.
When PSI1 is asserted, the VR0 is in single-phase CCM operation
with PWM1, or 2-phase CCM operation with PWM1 and 2, or 3,
as shown in Table 1. The number of operational phases is
configured by “NPSI” register, shown in Table 3. In PSI2/3/Decay
state, only single phase is in DCM/CCM operation, which is
programmed by the “DE” register; the opposite PWM 2, or 3
(depending upon configured maximum phase number as in
Table 1) of the PWM1 however will pull low at PWM1 high in CI
applications.
15
FN6861.0
December 22, 2010