ISL6364 Datasheet, PDF (16/44 Pages) Intersil Corporation – Dual 4-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6364
TABLE 3. PHASE DROPPING CONFIGURATION AT PSI1 AND
PSI2/3/DECAY
SICI NPSI CODE
PSI1 Mode
PSI2/3
& DECAY
0
0 SI1 SI, (N-1)-CI
1-Phase
1-Phase
0
1
SI2 SI, (N-2)-CI
2-Phase
1-Phase
1 0 CI1 2-Phase CI 1-Phase
1-Phase
1 1 CI2 2-Phase CI 2-Phase
1-Phase
NOTE: For 2-Phase CI option, the dropped coupled phase turns on LGATE
to circulate current when PWM1 is high.
The VR1 output can be disabled by pulling PWMS to VCC while the
respective address is released for use with a different VR controller.
For proper operation of VR0, the VR1’s respective pins should be
configured as described in “Disabling Output” on page 35.
While the controller is operational (VCC above POR, EN_VTT and
EN_PWR are both high, valid VID inputs), it can pull the PWM pins
to ~40% of VCC (~2V for 5V VCC bias) during various stages, such
as soft-start delay, phase shedding operation, or fault conditions
(OC or OV events). The matching driver's internal PWM resistor
divider can further raise the PWM potential, but not lower it
below the level set by the controller IC. The controller's PWM
outputs are directly compatible with Intersil drivers that require
5V PWM signal amplitudes. Drivers requiring 3.3V PWM signal
amplitudes are generally incompatible.
Diode Emulation Operation
To improve light efficiency, the ISL6364 can enter diode
emulation operation in PSI2/3 or Decay mode. Users however
should select Intersil VR12/IMVP7 compatible drivers: ISL6627
or ISL6625 for PSI# channel(s). The diode emulation should be
disabled if non-compatible power stages or drivers are used.
Switching Frequency
Both VR0 and VR1 can independently set switching frequency,
which is determined by the selection of the frequency-setting
resistor, R_T, which is connected from FS or FSS pin to GND or
VCC. Equation 4 and Figure 4 are provided to assist in selecting
the correct resistor value.
R_T
=
5_------⋅_---1---0---¹_---⁰_--
F_SW
(EQ. 4)
where F_SW is the switching frequency of each phase.
Independent frequency for VR0 and VR1 allows for cost,
efficiency, and performance optimization. Proximity between the
power trains of the two regulators imposed by the space-
constrained layouts can lead to cross-coupling. To minimize the
effect of cross-coupling between regulators, select operating
frequencies at least 50kHz apart.
SWITCHING FREQUENCY (Hz)
FIGURE 4. SWITCHING FREQUENCY vs RT
Current Sensing
The ISL6364 senses current continuously for fast response. The
ISL6364 supports inductor DCR sensing, or resistive sensing
techniques. The associated channel current sense amplifier uses
the ISEN inputs to reproduce a signal proportional to the inductor
current, I_L. The sense current, I_SEN, is proportional to the inductor
current. The sensed current is used for current balance, load-line
regulation, and overcurrent protection.
The internal circuitry, shown in Figures 5-6 and 9-10, represents
VR1’s channel or one channel of the VR0 output, respectively. For
VR0 output, the ISEN± circuitry is repeated for each channel, but
may not be active depending on the status of the PWM2, PWM3,
and PWM4 pins, as described in “PWM and PSI# Operation” on
page 15. The input bias current of the current sensing amplifier
is typically 60nA; less than 8.34kΩ input impedance (0.5mV
offset) is preferred to minimized the offset error, i.e., a larger C
value as needed.
INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed resistance,
as measured by the DCR (Direct Current Resistance) parameter.
Consider the inductor DCR as a separate lumped quantity, as
shown in Figure 5. The channel current I_L, flowing through the
inductor, will also pass through the DCR. Equation 5 shows the s-
domain equivalent voltage across the inductor V_L.
V_L(s) = I_L ⋅ (s ⋅ L + DCR)
(EQ. 5)
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 5.
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FN6861.0
December 22, 2010