ISL78268 Datasheet, PDF (4/33 Pages) Intersil Corporation – Integrated 2A sourcing

ISL78268
Functional Pin Description (Continued)
PIN NAME PIN #
DESCRIPTION
EN
9 This pin is a threshold-sensitive enable input for the controller. Connecting the power supply input to the EN pin through an
appropriate resistor divider provides a means to have input voltage UVLO. When EN pin is driven above 1.2V, the ISL78268 is active
depending on status of the internal POR, and pending fault states. Driving the EN pin below 1.1V will clear all fault states and the
ISL78268 will soft-start when reenabled.
PLL_COMP 10 This pin serves as the compensation node for the PLL. A second order passive loop filter connected between the PLL_COMP pin and
GND compensates the PLL feedback loop.
HIC/LATCH
11 This pin is used to select either HICCUP or LATCHOFF response for faults including output overvoltage, V_IN overvoltage, peak
overcurrent protection (OC2) and average overcurrent protection.
HIC/LATCH = HIGH to activate HICCUP fault response,
HIC/LATCH = LOW to have LATCHOFF fault response.
Either toggling EN pin or recycling VCC POR can reset the IC from LATCHOFF status.
CLKOUT
12 This pin provides a clock signal to synchronize with another ISL78268. The rising edge signal on the CLKOUT pin is delayed 180° from the
rising edge of UG to facilitate 2-phase interleaved operation using two ICs.
PGND
This Power GND pin provides the return path for the low-side MOSFET drive. Note this pin carries the noisy driving current and the
13
trace connected to the low-side MOSFET and PVCC decoupling capacitors should be as short as possible. Any sensitive analog signal
trace should not share common traces with this driving return path. Connect this pin directly to the ground copper plane and put
several vias as close as possible to this pin.
PVCC
Output of the internal linear regulator that provides bias for both high-side and low-side drives. The PVCC operating range is 4.75V
14 to 5.5V. A minimum 4.7µF ceramic capacitor should be used between PVCC and PGND for noise decoupling purpose. This capacitor
provides a noisy driving current and its ground pad should have several vias connecting to the ground copper plane.
LG
15 The low-side MOSFET gate drive output.
PH
16
Phase node. Connect this pin to the source of the high-side MOSFETs and the drain of the low-side MOSFETs. This pin represents the
return path for the high-side gate drive.
UG
17 High-side MOSFET gate drive output.
BOOT
18
This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the external
N-channel MOSFET. Place a 1µF ceramic capacitor between the BOOT and PH pins, and a switching diode from PVCC to BOOT.
Connect input rail to this pin. This pin is connected to the input of the internal linear regulator, generating the power necessary to
VIN
19 operate the chip. It is recommended the DC voltage applied to the VIN pin does not exceed 55V when the IC is switching. VIN can
stand up to 60V when IC is not switching.
ISEN1N
The ISEN1N pin is a negative potential input pin of the first current sense amplifier (CSA1). This amplifier senses the signal on the
20 current-sense resistor placed in series with the high-side MOSFET. The sensed current information is used for peak current mode
control and overcurrent protection.
ISEN1P 21 The ISEN1P pin is a positive potential input pin of the first current sense amplifier (CSA1).
ISEN2N
The ISEN2N pin is a negative potential input pin of the second current sense amplifier (CSA2). This amplifier senses the continuous
output inductor current either by DCR sensing method or using a sense resistor in series with the inductor for more accurate sensing.
22
The sensed current signal is used for 3 functions:
- Accurately limiting the average output current for constant output current control
- Achieve diode emulation
- Achieve average OCP (comparator at IMON/DE pin with 2V reference)
ISEN2P 23 The ISEN2P pin is a positive potential input pin of the second current-sense amplifier (CSA2).
This pin provides bias power for the IC analog circuitry. An RC filter is recommended between this pin and the bias supply (range of
VCC
24 4.75V to 5.5V, typically from PVCC). A minimum 1µF ceramic capacitor should be used between VCC and GND for noise decoupling
purposes.
EPAD
Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to a PCB large ground copper
plane that doesn’t contain noisy power flows. Put multiple vias (as many as possible) in this pad connecting to the ground copper plane
to help reduce the IC’s _JA.
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FN8657.3
December 12, 2014