ISL78268 Datasheet, PDF (21/33 Pages) Intersil Corporation – Integrated 2A sourcing

ISL78268
0.4V (typ), the switching frequency will change to the target
frequency gradually and the high-side MOSFET on-time will be
controlled by the PWM control loop. If the prebiased FB voltage is
above 0.4V (typ), the device starts up with the target switching
frequency. If FB voltage is >0.4V the time t₆ - t₇ is negligible.
t₆ - t₈: At t₆, COMP is above the peak current mode control ramp
offset, the drivers starts switching. Output voltage ramps up
while FB voltage is following SS ramp during this soft-start
period. At t₈, output voltage reaches the regulation level and FB
voltage reaches 1.6V (typ).
t₇ - t₁₀: SS pin voltage continues ramping up until it reaches SS
clamp voltage 3.4V (typ) at t_9. The soft-start period will be
completed at t₁₀ which is 0.5ms (typ) after the t_9. When the
soft-start completes, the device operates in the operation mode
selected by the IMON/DE configuration. If the Forced PWM mode
is selected, the device operates in full synchronous rectification.
If the Diode Emulation Mode (DE Mode) is selected, the device
will be able to operate in DE mode, i.e., turn-off low-side MOSFET
when the inductor current reaches zero to prevent the negative
current and improves the efficiency. At the end of soft-start
period t_10, the PGOOD open-drain follows the COMP and inductor
current ramp signal relations. Pin is released and will be pulled
up by the external resistor.
Enable
To enable the device, the EN pin needs to be driven higher than
1.2V (typ.) by the external enable signal or resistor divider
between VIN and GND. The EN pin has an internal 5MΩ (typ)
pull-down resistor. Also, this pin internally has a 5.2V (typ) clamp
circuit with 5kΩ (typ) resistor in series to prevent excess voltage
applied to the internal circuits. When applying the EN signal
using resistor divider from VIN, internal pull-down resistance
needs to be considered. Also the resistor divider ratio needs to be
adjusted as its EN pin input voltage may not exceed 5.2V.
To disable or reset all fault status, the EN pin needs to be driven
lower than 1.1V (typ). When the EN pin is driven to low, the
ISL78268 turns off all of the blocks to minimize the off-state
quiescent current.
VIN
Clock Generator and Synchronization
INTERNAL CLOCK FREQUENCY SETTING
The switching frequency is determined by the selection of the
frequency-setting resistor, R_FSYNC, connected from the FSYNC
pin to GND. Equation 1 and Figure 40 provide the relation
between R_FSYNC and switching frequency. For stable operation of
the device, it is recommended to set the f_SW between 50kHz to
1.1MHz.
R_FSYNC
=
2.5
x

10
¹⁰
x


-⁰----^.-⁵---
f_SW
–
5.0
X 10^–8_
(EQ. 1)
Where f_SW is the switching frequency of the device.
1400
1200
1000
800
600
400
200
0
0
50
100
150
200
250
300
R_FSYNC (kΩ)
FIGURE 40. R_FSYNC vs f_SW
Figure 41 shows the block diagram of the Clock Generator block.
The FSYNC pin is biased at 0.5V (typ). The 0.5V at FSYNC creates
a constant current with R_FSYNC. The current is fed to the internal
oscillator to generate the internal base clock. This internal base
clock is reshaped with the Phase Lock Loop (PLL) circuitry and
the output of PLL will be used as the main clock of the device.
VCC
FROM
EXTERNAL
EN CONTROL
VCC
EN
5k
+
5.2V
CLAMP
-
TO INTERNAL
CIRCUITS
5M
1.2V
FSYNC
FIGURE 39. ENABLE BLOCK
RFSYNC
INTERNAL
OSCILLATOR
INTERNAL BASE
CLOCK
+
0.5V
PLL
-
CLOCK
PFD _VCO
EXTERNAL
CLOCK
VIH(RISE) > 3.5V
VIL(FALL) < 1.5V
PLL_COMP
RPLLCMP
CPLLCMP1
CPLLCMP2
FIGURE 41. CLOCK GENERATOR AND EXTERNAL CLOCK
SYNCHRONIZATION BLOCK
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FN8657.3
December 12, 2014