ISL78268 Datasheet, PDF (22/33 Pages) Intersil Corporation – Integrated 2A sourcing

ISL78268
SYNCHRONIZATION WITH EXTERNAL CLOCK
The ISL78268 contains a PLL circuitry and has frequency
synchronization capability by simply connecting the FSYNC pin to
an external square pulse waveform.
The PLL block detects the rising edge of external clock and
synchronizes it with the rising edge of UG. The delay time of UG
rising from the external clock rising edge is 325ns (typ).
The FSYNC pin has special thresholds to detect the external
clock. The input high level of external clock should be higher than
3.5V and low level should be lower than 1.5V.
When continuous external clock pulse is applied while operating
with internal clock which is determined by R_FSYNC, this device
synchronizes with the external clock gradually and continues its
switching. However, when the external clock is removed for a certain
period (~6ms), the device will stop its switching and restart from the
initialization/soft-start process after about a 50ms interval.
The PLL is compensated with a series connected resistor and
capacitor (R_PLLCMP and C_PLLCMP) from the PLL_COMP pin to
GND and a capacitor (C_PLLCMP2) from PLL_COMP to GND. For
stable operation, recommended to set R_PLLCMP = 3.24kΩ,
C_PLLCMP1 = 6.8nF, C_PLLCMP2 = 1nF. The typical lock time for this
case will be around 0.8ms.
The CLKOUT pin provides a square pulse waveform at the
switching frequency. The amplitude is GND to VCC with
270ns (typ) pulse width, and the rising edge is 180° shifted from
the rising edge of UG.
Soft-Start
Soft-start is implemented by an internal 5µA current source
charging the soft-start capacitor (C_SS) at SS to GND. The voltage
on the SS pin controls the reference voltage for the FB pin during
soft-start. When starting up the system while the output voltage
is remaining (prebiased), a prebias circuit charges the C_SS
capacitor to the same voltage as FB voltage before soft-start
begins. This allows more accurate correlation between the
soft-start ramp time and the output voltage.
Assuming no prebiased output condition, the soft-start ramp
time is:
t_SS
=
V_R
EF
-^C----^S---^S--
5A
(EQ. 2)
Where V_REF is the 1.6V reference.
Assuming no load condition, the average inductor current
I_{L_softstart} to charge the output capacitors from 0V to final
regulation voltage within soft-start time t_SS can be estimated as:
I_Lsoftstart
=
V_OU
T
C_{----O----U----T}
t_SS
(EQ. 3)
If start-up with full load is required, the total inductor average
current at the soft-start period is the sum of full load current and
I_{L_softstart}. Based on this consideration, enough soft-start time
should be set to make sure overcurrent protection is not tripped.
At the beginning of soft-start, if the prebiased V_FB voltage is
lower than 0.4V (typ), the device is forced to switch at 50kHz (typ)
with minimum on-time of high-side MOSFET. When V_FB reaches
0.4V (typ) or higher, the device operates with normal switching
frequency and on-time. If the prebiased VFB voltage is higher
than 0.4V (typ) at the starting of soft-start, the device starts with
normal switching frequency from the beginning.
VCC
SS
CSS
VOUT
FB
5µA
3.4V
CLAMP
-+
SOFT-START
+
CONTROL
LOGIC
-
0.4V
SS_Prebias
+
-
SS_DONE
TO PWM CONTROL
& PGOOD CONTROL
0.4V
+
+ Gm
-
VREF = 1.6V
COMP
TO PWM COMPARATOR
COMP
FIGURE 42. SOFT-START BLOCK
The soft-start period will be finished when the SS pin voltage
reaches its clamp voltage (3.4V typ) with a 0.5ms (typ) additional
interval. At the end of soft-start period, the pull-down of the
PGOOD pin will be released and this pin will be pulled up by
external resistor, which will be biased to VCC or external logic
supply level.
While in soft-start period, the device operates in Diode Emulation
mode to prevent undesired negative current at inductor from
output. In this period, regardless of the configuration of IMON/DE
pin, i.e., either Forced PWM mode or Diode Emulation mode is
selected, only the high-side MOSFET will be switched and
low-side MOSFET will be kept off.
Bootstrap for High-side NMOS Drive
To turn on the high-side MOSFET properly, the ISL78268 employs
a bootstrap circuit using an external boot capacitor (C_BOOT) and
diode (D_BT). At the time the high-side MOSFET turns off, to
maintain the current on the inductor, the PH node will go down to
GND level at low-side MOSFET turn on. While in this low-side
MOSFET on period, the diode connected from PVCC to boot
capacitor will be forward biased and charge up the boot
capacitor. When the low-side MOSFET is turned off and the
high-side MOSFET is turned on after dead-time, the PH node goes
up to VIN level and the BOOT pin bias is VIN + PVCC - V_F to drive
the high-side driver circuitry.
BOOT REFRESHING
In order to keep sufficient supply voltage for the high-side driver
circuit operation, the ISL78268 has a boot-refreshing circuit.
When the boot capacitor voltage becomes lower than 3.3V (typ),
the low side transistor is forced to turn on with its minimum on
time to charge the boot capacitor. The boot refreshing will occur
at the beginning of soft-start and pulse skipping operation at very
light load conditions.
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FN8657.3
December 12, 2014