ISL78268 Datasheet, PDF (11/33 Pages) Intersil Corporation – Integrated 2A sourcing

ISL78268
Electrical Specifications Refer to the Block Diagram (page 6) and Typical Application Schematics (page 7). Operating conditions unless
otherwise noted: V_IN = 12V, V_PVCC = 5.2V and V_VCC = 5.2V, EN = 5.0V, T_A = -40°C to +125°C. Typicals are at T_A = +25°C.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7) UNITS
POWER-ON RESET (for both PVCC and VCC)
Rising V_PVCC/VCC POR Threshold
Falling V_PVCC/VCC POR Threshold
V_PVCC/VCC POR Hysteresis
Phase Lock Loop Locking Time
EN
V_{PORH_RISE}
4.35 4.55 4.75 V
V_{PORL_FALL}
4.1 4.15 4.3
V
V_{PORL_HYS}
0.4
V
t_{PLL_DLY} From POR to Initiation of soft-start.
0.8
ms
R_PLLCMP = 3.24k, C_PLLCMP1 = 6.8nF,
C_PLLCMP2 = 1nF, R_FSYNC = 40.2k, f_SW = 300kHz
Enable Threshold
Input Resistance
V_ENH
V_ENL
V_{EN_HYS}
Rising
Falling
Hysteresis
EN = 4V
EN = 6V
1.1
1.2
1.3
V
1.04 1.14 1.24 V
60
mV
3000 5000 8000 _kΩ
5
kΩ
OSCILLATOR
PWM Switching Frequency
Switching Frequency Range
Synchronization Range at FSYNC
CLKOUT
F_OSC
R_FSYNC = 249kΩ (0.1%)
R_FSYNC = 40.2kΩ (0.1%)
R_FSYNC = 10kΩ (0.1%)
T_A = +25°C, V_IN = 12V
T_A = +25°C, V_IN = 12V
47.5 50 52.5 kHz
285 300 315 kHz
1036 1100 1155 kHz
50
1100 kHz
50
1100 kHz
High Level CLKOUT Output Voltage
Low Level CLKOUT Output Voltage
Output Pulse Width
Phase Shift from UG Rising Edge to CLKOUT
Pulse Rising Edge
CLKOUT_H
CLKOUT_L
I_CLKOUT = 500µA
I_CLKOUT = -500µA
C_CLKOUT = 100pF
UG = OPEN, C_CLKOUT = OPEN
VCC-0.4 VCC-0.1
V
0.1
0.4
V
270
ns
180
°
SYNCHRONIZATION (FSYNC pin)
Input High Threshold
VIH
3.5
V
Input Low Threshold
VIL
1.5
V
Input Pulse Width - Rise_To_Fall
20
20,000 ns
Input Pulse Width - Fall_To_Rise
20
20,000 ns
Delay from Input Pulse Rising to UG Rising Edge
UG = OPEN
325
ns
SOFT-START
Soft-Start Current
Soft-Start Pin PreBias Voltage Range
Soft-Start PreBias Voltage Accuracy
Soft-Start Clamp Voltage
REFERENCE VOLTAGE
Reference Accuracy
FB Pin Input Bias Current
ERROR AMPLIFIER
Transconductance Gain
COMP Output Impedance
Unity Gain Bandwidth
I_SS
V_{SS_PRE}
V_SSCLAMP
V_SS = 0V
In prebias output condition; V_{SS_PRE} = V_FB
V_FB = 500mV
Measured at FB pin
V_FB = 1.6V
C_{CMP =} 100pF from COMP pin to GND
4.5
5
5.5 µA
0
1.6
V
-25
25 mV
3
3.4
3.8
V
1.584 1.6 1.616 V
-0.05
0.05 µA
2
ms
10
MΩ
11
MHz
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FN8657.3
December 12, 2014