ISL78268 Datasheet, PDF(20/33 Page) Intersil Corporation

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ISL78268 Datasheet, PDF (20/33 Pages) Intersil Corporation – Integrated 2A sourcing

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ISL78268

Operation Description

The ISL78268 is an automotive graded (AEC-Q100 Grade-1)

single-phase synchronous buck controller with integrated

high/low side 2/3A MOSFET drivers. It supports a wide operating

input voltage range of 5V to 55V and up to 60V at VIN when not

switching. The device also provides the features of selectable

Diode Emulation mode for the higher efficiency operation in light

load conditions, average constant output current controls, and

several protection features such as input overvoltage protection,

output overvoltage protection, cycle-by-cycle current limit and

protections, and thermal protection. Details of the functions are

described in the following.

Synchronous Buck

In order to improve the efficiency, the ISL78268 employs

synchronous buck architecture. In a synchronous buck, the LG

output drives the synchronous low-side MOSFET, which replaces

the freewheeling diode and improves the power losses by the

voltage drop of the freewheeling diode while the high-side

MOSFET is off. The LG signal is complementary to the UG signal.

The UG signal is powered from a charge pump that generates a

voltage between BOOT and PH. An external diode from PVCC to

BOOT charges an external capacitor between BOOT and PH when

LG is high and PH is low. The capacitor provides the power to

drive UG high. BOOT rises with PH and maintains the voltage to

drive UG as the bootstrap diode is reverse biased.

Adaptive Dead-Time Control

The UG and LG drivers are designed to have an adaptive

dead-time algorithm that optimizes operation with varying

MOSFET conditions. In this algorithm, the device detects the off

timing of external MOSFETs which is turning off via the gate

driver output voltage. The ISL78268 adds internally fixed 55ns

dead-time before turning on the target gate driver. This algorithm

helps to prevent shoot-through current at the switching of

external MOSFETs and also optimizes the total dead-time to

maximize the efficiency.

Operation Initialization and Soft-Start

Prior to the converter initialization, VIN and VCC need to be

supplied within the valid voltage range and the EN pin needs to be

biased to logic high. When these conditions are provided, the

controller begins soft-start. Once the output voltage is within the

proper window of output regulation, VPGOOD is asserted logic high.

Figure 38 shows the ISL78268 internal start-up timing diagram

from the power-up to soft-start and valid PGOOD assertion.

As shown on Figure 38, there are 5 time intervals before the

soft-start is initialized, they are specified as t1through t5. After

soft-start is initiated, there are 5 time intervals indicated as t5

through t10. The descriptions for each time interval are as

follows:

t1 - t2: The internal enable comparator holds the ISL78268 in

shutdown until the EN pin voltage (VEN) rises above 1.2V (typ) at

the time of t1. During t1 - t2 the internal LDO output voltage at the

PVCC pin (VPVCC) will gradually increase until t2 when it reaches

the internal Power-On Reset (POR) rising threshold which is

4.5V(typ).

1.2V

POR_R PVCC/VCC

PLLCOMP

CLKOUT

COMP

VFB

COMP_Ramp_Offset

VFB = 0.4V

PGOOD

t1 t2 t3

t4 t5 t6 t7

t9 t10

FIGURE 38. CIRCUIT INITIALIZATION AND SOFT-START

t2 - t3: During t2 - t3 time, the ISL78268 will go through a

self-calibration process to determine the pin connections

(HIC/LATCH, IMON/DE) for the operation mode selections. The

time duration for t2 - t3 is typically 170Âµs.

t3 - t4: During this period, the ISL78268 will wait until the internal

PLL circuit is locked to the preset oscillator frequency set by the

resistor on FSYNC or the external clock at FSYNC. When PLL

locking is achieved at t4, the oscillator will generate output at the

CLK_OUT pin. The time duration for t3 - t4 depends on PLL_COMP

pin configuration. The PLL is compensated with a series

resistor-capacitor RPLLCMP, CPLLCMP1 from the PLL_COMP pin to

GND and a capacitor CPLLCMP2 from PLL_COMP to GND. Typical

CPLLCMP2 = 1nF. With this PLL_COMP compensation, the time

duration for t3 - t4 is around 0.8ms.

t4 - t5: After the PLL locks the frequency at t4, the system is

preparing to soft-start. The ISL78268âs unique feature will

prebias the VSS based on VFB voltage during this time. The

duration time for t4 - t5 is around 50Âµs. During t4 - t5 drivers

remain off.

t5 - t6: After t5, the soft-start circuit starts to ramp up from the

prebiased VFB. At the same time, the COMP pin voltage starts to

ramp up also. The UG driver will be enabled at t5. However,

before t6, COMP is still below the peak current mode control

ramp offset, the drivers will not be switching. During soft-start

period t5 - t10, the device will operate with Diode Emulation

mode and keep LG driver off.

t6 - t7: If the FB voltage (VFB) is below 0.4V (typ), the device

operates at fixed minimum frequency (50kHz (typ)) with

minimum high-side MOSFET on-time. When VFB reaches

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December 12, 2014

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