ISL78268 Datasheet, PDF (3/33 Pages) Intersil Corporation – Integrated 2A sourcing

Pin Configuration
ISL78268
ISL78268
(24 LD 4x4 QFN)
TOP VIEW
24 23 22 21 20 19
SLOPE 1
18 BOOT
FB 2
17 UG
COMP 3
SS 4
EPAD
16 PH
15 LG
IMON/DE 5
14 PVCC
PGOOD 6
13 PGND
7 8 9 10 11 12
Functional Pin Description
PIN NAME PIN #
DESCRIPTION
SLOPE
1 This pin programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE pin to GND. Please refer
to “Adjustable Slope Compensation” on page 24 for how to choose this resistor value.
FB
2 The inverting input of the transconductance amplifier. A resistor divider must be placed between the FB pin and the output rail to
set the output voltage.
COMP
3 The output of the transconductance amplifier. Place the compensation network between the COMP pin and GND for compensation loop
design.
SS
4 Use this pin to set up the desired soft-start time. A capacitor placed from SS to GND will set up the soft-start ramp rate and in turn
determine the soft-start time.
IMON/DE
IMON/DE is a bifunctional pin as either the average current monitor/protection or switching mode selection (Diode Emulation (DE)
mode or Forced PWM mode).
1. If IMON/DE pin is connected to VCC (higher than VCC - 0.7V), the device operates in Forced PWM mode and the average current
monitoring/limiting feature is disabled.
2. If a resistor (and a filter capacitor in parallel) is connected between IMON/DE and GND, the device operates in DE mode and
5
the average current monitoring/limiting feature is enabled. A current which is proportional to the current sensed at I_SEN2 is
sourced from the IMON/DE pin. With an R/C network at the IMON/DE pin to GND, the voltage at IMON/DE pin describes
average output current.
When average current monitoring/limiting feature is enabled and DE mode is selected;
1. If IMON/DE is higher than 2V, the device enters Average Current Protection mode with the hiccup/latch-off as the fault response.
2. If IMON/DE reaches to 1.6V, the device enters the Average Constant Current control loop.
3. If the IMON/DE pin voltage is lower than 1.6V (typ), the device operates as a normal buck regulator in DE mode.
PGOOD
6 Provides an open-drain Power-Good signal. When the output voltage is within +15/-12% of the nominal output regulation point and
soft-start is completed, the internal PGOOD open-drain transistor is open. It will be pulled low once output UV/OV or input OV conditions
are detected. Requires pull-up resistor connecting to VCC.
FSYNC
7 The oscillator switching frequency is adjusted with a resistor from this pin to GND. The internal oscillator locks to the rising edge of
a square pulse waveform if this pin is driven by an external clock. There is a 325ns delay from the FSYNC pin’s input clock rising
edge to UG rising edge.
SGND
8 Signal ground pin; the reference of internal analog circuits. Connect this pin to a large quiet copper ground plane. In PCB layout
planning, avoid having switching current flowing into the SGND area (including the IC PAD that is connected to the quiet large copper
ground plane also).
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FN8657.3
December 12, 2014