ISL6322G Datasheet, PDF (34/39 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers, I2C Interface and Phase Dropping

ISL6322G
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. The regulated converter is
accurately modeled as a voltage-mode regulator with two
poles at the L-C resonant frequency and a zero at the ESR
frequency. A type III controller, as shown in Figure 23,
provides the necessary compensation.
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f_HF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f_HF = 10f₀, but it can be
higher if desired. Choosing f_HF to be lower than 10f₀ can
cause problems with too much phase shift below the system
bandwidth.
C₂
R_C ^CC
COMP
C₁
R₁
R_FB
FB
ISL6322G
VDIFF
FIGURE 22. COMPENSATION CIRCUIT
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 36, R_FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 36.
R₁
=
R_FB
⋅ ------------C------^â‹---E----S-----R-------------
L ⋅ C – C ⋅ ESR
C₁
=
-----L-----^â‹---C-----^–-----C------^â‹---E----S-----R--
R_FB
C₂
=
----------------------------------------------V-----^I--^N------------------------------------------------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_P-P
R_C
=
-V----^P----^P-----^â‹---^⎝⎛---2----^π---^⎠⎞---²-----^â‹---f--⁰----^â‹---f--^H----^F-----^â‹---L-----^â‹---C-----^â‹---R-----^F----^B--
V_IN ^{⋅ (2 ⋅ π ⋅ f}_HF ^{⋅ L ⋅ C–1)}
C_C
=
---------------V-----^I-^N------^â‹---⁽--2-----^â‹---^π-----^â‹---f--^H----^F-----^â‹-------L-----^â‹---C----^–----1---⁾----------------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_P-P
(EQ. 36)
In Equation 36, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_P-P is the
peak-to-peak sawtooth signal amplitude as described in
“Electrical Specifications” on page 6.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔV_MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by the amount
specified in Equation 37.
ΔV
≈
ESL
⋅
-d---i
dt
+
ESR
⋅
ΔI
(EQ. 37)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
page 10 and Equation 38), a voltage develops across the
34
FN6715.0
May 22, 2008