ISL6322G Datasheet, PDF (28/39 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers, I2C Interface and Phase Dropping

I²C Read and Write Protocol
Write to a Single Register
S slave_addr + W A
reg_addr
Write to Both Registers
S slave_addr + W A
0000_0000
ISL6322G
A
reg_data
AP
A reg_RGS1_data A reg_RGS2_data A P
Read from a Single Register
S slave_addr + W A
reg_addr
Read from Both Registers
S slave_addr + W A
0000_0000
A P S slave_addr + R A
reg_data
NP
A P S slave_addr + R A reg_RGS1_data A reg_RGS2_data N P
Driven by Master
S = START Condition
A = Acknowledge
Driven by ISL6322
P = STOP Condition
N = No Acknowledge
Reading from the Internal Registers
The ISL6322G has the ability to read from both registers
separately or read from them consecutively. Prior to reading
from an internal register, the master must first select the
desired register by writing to it and sending the register’s
address byte. This process begins by the master sending a
control byte with the R/W bit set to 0, indicating a write. Once
it receives an Acknowledge from the ISL6322G, it sends a
register address byte representing the internal register it
wants to read from (0000_0000 for RGS1 or 0000_0001 for
RGS2). The ISL6322G will respond with an Acknowledge.
The master must then respond with a Stop condition. After
the Stop condition, the master follows with a new Start
condition, and then sends a new control byte with the R/W
bit set to 1, indicating a read. The ISL6322G will then
respond by sending the master an Acknowledge, followed by
the data byte stored in that register. The master must then
send a Not Acknowledge followed by a Stop command,
which will complete the read transaction.
It is also possible for both registers to be read consecutively.
To do this the master must read from register RGS1 first.
This transaction begins with the master sending a control
byte with the R/W bit set to 0. If it receives an Acknowledge
from the ISL6322G, it sends the register address byte
0000_0000, representing the internal register RGS1. The
ISL6322G will respond with an Acknowledge. The master
must then respond with a Stop condition. After the Stop
condition the master follows with a new Start condition, and
then sends a new control byte with the R/W bit set to 1,
indicating a read. The ISL6322G will then respond by
sending the master an Acknowledge, followed by the data
byte stored in register RGS. The master must then send an
Acknowledge, and after doing so, the ISL6322G will respond
by sending the data byte stored in register RGS2. The
master must then send a Not Acknowledge followed by a
Stop command, which will complete the read transaction.
Resetting the Internal Registers
The ISL6322G’s two internal I²C registers always initialize to
0000_0000 when the controller first receives power. Once
the voltage on the VCC pin rises above the POR rising
threshold level, these registers can be changed at any time
via the I²C interface. If the voltage on the VCC pin falls
below the POR falling threshold, the internal registers are
automatically reset to 0000_0000.
It is possible to reset the internal registers without powering
down the controller and without requiring the controller to
stop regulating and soft-start again. This can be done by one
of two methods. The first method is to simply write to the
internal registers over the I²C interface to be 0000_0000.
The other method is pull the voltage on the SS/RST/A0 pin
down below 0.4V. This will immediately reset the internal
registers to 0000_0000 and will not stop the controller from
regulating the output voltage or cause soft-start to recycle.
TABLE 8. REGISTER RGS1 (VOLTAGE MARGINING
OFFSET)
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
V_OFFSET
X X VO5 VO4 VO3 VO2 VO1 VO0 (mV)
x
x
0
0
0
0
0
0
0.0
x
x
0
0
0
0
0
1
12.5
x
x
0
0
0
0
1
0
25.0
x
x
0
0
0
0
1
1
37.5
x
x
0
0
0
1
0
0
50.00
x
x
0
0
0
1
0
1
62.5
x
x
0
0
0
1
1
0
75.0
x
x
0
0
0
1
1
1
87.5
x
x
0
0
1
0
0
0
100.0
x
x
0
0
1
0
0
1
112.5
28
FN6715.0
May 22, 2008