ISL6322G Datasheet, PDF (32/39 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers, I2C Interface and Phase Dropping

ISL6322G
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q_rr, it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P_UP,3.
P_UP,3 = V_IN ⋅ Q_rr ⋅ f_S
(EQ. 25)
Finally, the resistive part of the upper MOSFET is given in
Equation 26 as P_UP,4.
P_UP,4 ≈ r_DS(ON) ⋅ d ⋅
⎛
⎜
⎝
-I-^M---⎟⎞
N⎠
2
+
I--_P-------P2--
12
(EQ. 26)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results from
Equations 23, 24, 25 and 26. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three drivers
in the controller package, the total power dissipated by all three
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W at
room temperature. See “Layout Considerations” on page 36 for
thermal transfer improvement suggestions.
When designing the ISL6322G into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P_{Qg_TOT}, due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 27 and 28, respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
(EQ. 27)
P _{Q g _Q1}
=
3_--
2
⋅
Q_G
1
⋅
PVC
C
⋅
F_SW
⋅
N_Q1
⋅
N_PH
A
S
E
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ F_SW ⋅ N_Q2 ⋅ N_PHASE
.
I_DR
=
⎝⎛ ^32--
⋅
Q_G1
⋅
N_Q1
+
Q_G2
⋅
N_Q
⎞
2⎠
⋅ N_PHASE ⋅ F_SW + I_Q
(EQ. 28)
In Equations 27 and 28, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power loss;
the gate charge (Q_G1 and Q_G2) is defined at the particular gate
to source drive voltage PVCC in the corresponding MOSFET
data sheet; I_Q is the driver total quiescent current with no load
at both drive outputs; N_Q1 and N_Q2 are the number of upper
and lower MOSFETs per phase, respectively; N_PHASE is the
number of active phases. The I_Q*VCC product is the quiescent
power of the controller without capacitive load and is typically
75mW at 300kHz.
PVCC
BOOT
R_HI1
R_LO1
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
D
C_DS
Q1
PHASE
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
LGATE
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P_{DR_UP}, the lower drive path resistance,
P_{DR_UP}, and in the boot strap diode, P_BOOT.
P_DR = P_{DR_UP} + P_{DR_LOW} + P_BOOT + (I_Q ⋅ VCC)
P_BOOT
=
-^P----^Q----^g----^_--^Q-----¹-
3
(EQ. 29)
P _{D R _UP}
=
⎛
⎜
⎝
-------------^R-----^H----^I--¹--------------
R_HI1 + R_EXT1
+
-_R----_L---_O-----₁^R----+-^L---^O-_R----¹-_E----_X----_T---₁- _{⎠⎟⎞}
⋅
P_{-----Q----g----_--Q-----1-}
3
P _{D R _LOW}
=
⎛
⎜
⎝
-------------^R-----^H----^I--²--------------
R_HI2 + R_EXT2
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^- _{⎠⎟⎞}
⋅
P_{-----Q----g----_---Q----2-}
2
R_EXT1
=
R_G1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G2
+
R_{-----G-----I-2--}
N_Q2
32
FN6715.0
May 22, 2008