ISL6322G Datasheet, PDF (24/39 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers, I2C Interface and Phase Dropping

ISL6322G
conditions exist. This pin should be tied to a +5V source
through a resistor.
During shutdown and soft-start PGOOD pulls low and
releases high after a successful soft-start and the output
voltage is operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected or when the controller is disabled by a reset from
EN, POR, or one of the no-CPU VID codes. In the event of
an overvoltage or overcurrent condition, the controller
latches off and PGOOD will not return high until after a
successful soft-start. In the case of an undervoltage event,
PGOOD will return high when the output voltage returns to
within the undervoltage.
120µA OR
240µA
I_SEN1+I_SEN2
-
OCP
+
VDAC
I²C OVP
REGISTER
VRSEL
+175mV,
+250mV,
+350mV
V_OVP
-
OCL
+
170µA
I_SEN1
REPEAT FOR
EACH CHANNEL
+
OCP
-
IOUT
V_OCP
SOFT-START, FAULT
AND CONTROL LOGIC
VSEN
+
x1
-
RGND
-
OV
+
-
UV
+
PGOOD
VDIFF
0.60 x DAC _{ISL6322G INTERNAL CIRCUITRY}
FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY
Undervoltage Detection
The undervoltage threshold is set at 60% of the VID code.
When the output voltage (VSEN - RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 70% of the VID code.
Overvoltage Protection
The ISL6322G constantly monitors the sensed output voltage
on the VDIFF pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level
actions are taken by the ISL6322G to protect the
microprocessor load. The overvoltage protection trip level
changes depending on what mode of operation the controller
is in and what state the I²C registers and the VRSEL pin are
in. Tables 6 and 7 list what the OVP trip levels are under all
conditions (refer beginning on page 24 for details of
controlling OVP thresholds with I²C).
At the inception of an overvoltage event LGATE1 and
LGATE2 are commanded high and the PGOOD signal is
driven low. This turns on the all of the lower MOSFETs and
pulls the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high and
until VDIFF falls 100mV below the OVP threshold that
tripped the overvoltage protection circuitry. The ISL6322G
will continue to protect the load in this fashion as long as the
overvoltage condition recurs.
Once an overvoltage condition ends, the ISL6322G latches
off and must be reset by toggling EN, or through POR,
before a soft-start can be re-initiated.
TABLE 6. INTEL VR10 AND VR11 OVP THRESHOLDS
MODE OF
OPERATION
DEFAULT
ALTERNATE
Soft-Start
(t_D1 and t_D2)
1.280V and
VDAC + 250mV
(higher of the two)
1.280V and
VDAC + 175mV
(higher of the two)
Soft-Start
(t_D3 and t_D4)
Normal Operation
VDAC + 250mV
VDAC + 250mV
VDAC + 175mV
VDAC + 175mV
TABLE 7. AMD OVP THRESHOLDS
MODE OF
OPERATION
DEFAULT
ALTERNATE
Soft-Start
2.200V and
VDAC + 250mV
(higher of the two)
2.200V and
VDAC + 175mV
(higher of the two)
Normal Operation
VDAC + 250mV
VDAC + 175mV
One exception that overrides the overvoltage protection
circuitry is a dynamic VID transition in AMD modes of
operation. If a new VID code is detected during normal
operation, the OVP protection circuitry is disabled from the
beginning of the dynamic VID transition, until 50µs after the
internal DAC reaches the final VID setting. This is the only
time during operation of the ISL6322G that the OVP circuitry
is not active.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6322G is designed to protect the load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10kΩ resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
24
FN6715.0
May 22, 2008