ISL6322G Datasheet, PDF (26/39 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers, I2C Interface and Phase Dropping

ISL6322G
This is accomplished by continuously comparing the sensed
currents of each channel with a constant 170µA OCL
reference current as shown in Figure 14. If a channel’s
individual sensed current exceeds this OCL limit, the UGATE
signal of that channel is immediately forced low, and the
LGATE signal is forced high. This turns off the upper
MOSFET(s), turns on the lower MOSFET(s), and stops the
rise of current in that channel, forcing the current in the
channel to decrease. That channel’s UGATE signal will not
be able to return high until the sensed channel-current falls
back below the 170µA reference.
I²C Bus Interface
The ISL6322G includes an I²C bus interface which allows
for user programmability of five of the controller’s operating
parameters. The operating parameters that can be adjusted
through the I²C are:
1. Number of Phases Firing: Selects whether the
controller should run in single phase or 2-phase mode.
The EN_PH2 pin must be tied low for the number of
phases firing to be controlled by the I²C bus interface.
2. Voltage Margining Offset: The output voltage can be
positively offset up to +787.5mV in 12.5mV increments.
3. Adaptive Deadtime Control: Selects between LGATE
Detect and PHASE Detect deadtime control schemes as
described in the “User Selectable Adaptive Deadtime
Control Techniques” on page 21.
4. Overvoltage Trip Level: Selects the overvoltage
protection trip threshold as described in the “Overvoltage
Protection” on page 24.
5. Switching Frequency: The switching frequency can be
increased by a fixed +15% or +30%, or can be decreased
by -15% or -30%.
To adjust these five parameters, data transmission from the
main microprocessor to the ISL6322G and vice versa must
take place through the two wire I²C bus interface. The two
wires of the I²C bus consist of the SDA line, over which all data
is sent, and the SCL line, which is a clock signal used to
synchronize sending/receiving of the data.
Both SDA and SCL are bidirectional lines, externally connected
to a positive supply voltage via a pull-up resistor. Pull-up
resistor values should be chosen to limit the input current to
less then 3mA. When the bus is free, both lines are HIGH. The
output stages of ISL6322G have an open drain/open collector
in order to perform the wired-AND function. Data on the I²C bus
can be transferred up to 100kbps in the standard-mode or up to
400Kbps in the fast-mode. The level of logic “0” and logic “1” is
dependent on associated value of V_DD as per the “Electrical
Specifications” table on page 6. One clock pulse is generated
for each data bit transferred. The ISL6322G is a “SLAVE only”
device, so the SCL line must always be controlled by an
external master.
It is important to note that the I²C interface of the ISL6322G
only works once the voltage on the VCC pin has risen above
the POR rising threshold. The I²C will continue to remain
active until the voltage on the VCC pin falls back below the
falling POR threshold level.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW. Refer
to Figure 16.
SDA
SCL
DATA LINE CHANGE
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 16. DATA VALIDITY
START and STOP Conditions
As shown in Figure 17, a START (S) condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The STOP (P) condition is a LOW to HIGH transition on the
SDA line while SCL is HIGH. A STOP condition must be sent
before each START condition.
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
FIGURE 17. START AND STOP WAVEFORMS
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB) and the least significant bit last (LSB).
Acknowledge
Each address and data transmission uses 9-clock pulses.
The ninth pulse is the acknowledge bit (A). After the start
condition, the master sends 7-slave address bits and a R/W
bit during the next 8-clock pulses. During the ninth clock
pulse, the device that recognizes its own address holds the
data line low to acknowledge. The acknowledge bit is also
used by both the master and the slave to acknowledge
receipt of register addresses and data as described as
follows.
26
FN6715.0
May 22, 2008