ISL6322G Datasheet, PDF (23/39 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers, I2C Interface and Phase Dropping

ISL6322G
TD1 is a fixed delay with the typical value as 1.40ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
During t_D2 and t_D4, ISL6322G digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R_SS from SS pin to GND. The
second soft-start ramp time t_D2 and t_D4 can be calculated
based on Equations 15 and 16:
t_D2 = -16---.-.-12----5^â‹---R--_â‹---2^S---5-^S--(μs)
(EQ. 15)
t_D4(2)
=
--⁽--V-----^V----^I-^D------^–----1----.-1----⁾-----^â‹---R-----^S---^S--
6.25 ⋅ 25
(μs)
(EQ. 16)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time t_D2 will be 704µs and the
second soft-start ramp time t_D4 will be 256µs.
NOTE: If the SS pin is grounded, the soft-start ramp in t_D2
and t_D4 will be defaulted to a 6.25mV step frequency of
330kHz.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay t_D5. The typical value
for t_D5 is 440µs.
V_OUT, 500mV/DIV
t_DA
t_DB
t_DC
EN_VTT
PGOOD
500µs/DIV
FIGURE 12. AMD SOFT-START WAVEFORMS
AMD Soft-Start
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of three periods, as shown
in Figure 12. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period t_DA. After this delay period the ISL6322G will
begin ramping the output voltage to the desired DAC level at
a fixed rate of 6.25mV per step, with a stepping frequency of
330kHz. The amount of time required to ramp the output
voltage to the final DAC voltage is referred to as TDB, and
can be calculated as shown in Equation 17.
TDB
=
------------¹-------------
330 × 10³
⋅
⎛
⎝
0^----.^-V0----V0^---6^-I--D2^----5^{--⎠⎞}
(EQ. 17)
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay t_DC. The typical value
for t_DC can range between 1.5ms and 3.0ms.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
V_OUT (0.5V/DIV)
GND>
EN (5V/DIV)
t1 t2
t3
FIGURE 13. SOFT-START WAVEFORMS FOR
ISL6322G-BASED MULTIPHASE CONVERTER
Pre-Biased Soft-Start
The ISL6322G also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level.
Fault Monitoring and Protection
The ISL6322G actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 14
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6322G is regulating the
output voltage within the proper levels, and whether any fault
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FN6715.0
May 22, 2008