ISL6322G Datasheet, PDF (10/39 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers, I2C Interface and Phase Dropping

ISL6322G
LGATE1 and LGATE2
These pins are used to control the lower MOSFETs. Connect
these pins to the corresponding lower MOSFETs’ gates.
EN_PH2
This pin is a digital logic input which tells the controller to
operate in single phase or 2-phase mode. The number of
active phases can be changed while the controller is
operating by changing the state of this pin. Tying this pin
high commands the part to operate in single phase mode
only. If EN_PH2 is tied low the part can operate in either
single phase or 2-phase mode depending on the state of
Bit 6 of I²C register 2. The default I²C setting is 2-phase
mode, so if Bit 6 of register 2 is not changed tieing EN_PH2
low commands the controller to operate in 2-phase mode.
If EN_PH2 is tied high the controller will ignore the state of
bit 6 in register 2 and will not allow the I²C interface to
control the number of channel’s firing.
SS/RST/A0
This pin has three different functions associated with it. The
first is that a resistor (R_SS), placed from this pin to ground, or
VCC, will set the soft-start ramp slope for the Intel DAC
modes of operation. Refer to Equations 15 and 16 for proper
resistor calculation.
The second function of this pin is that it selects which of the
two 8-bit Slave I²C addresses the controller will use.
Connecting the R_SS resistor on this pin to ground will
choose slave address one(1000_110x), while connecting
this resistor to VCC will select slave address
two(1000_111x).
The third function of this pin is a reset to the I²C registers.
During normal operation of the part, if this pin is ever
grounded, all of the I²C registers are reset to 0000_0000. An
open drain device is recommended as the means of
grounding this pin for resetting the I²C registers.
SCL
Connect this pin to the clock signal for the I²C bus, which is
a logic level input signal. The clock signal tells the controller
when data is available on the I²C bus.
SDA
Connect this pin to the bidirectional data line of the I²C bus,
which is a logic level input/output signal. All I²C data is sent
over this line, including the address of the device the bus is
trying to communicate with, and what functions the device
should perform.
PGOOD
During normal operation PGOOD indicates whether the
output voltage is within specified overvoltage and
undervoltage limits. If the output voltage exceeds these limits
or a reset event occurs (such as an overcurrent event),
PGOOD is pulled low. PGOOD is always low prior to the end
of soft-start.
NC
These are “no connect” pins. They should be left floating.
Operation
Multiphase Power Conversion
Microprocessor load current profiles have changed to the
point that using single-phase regulators is no longer a viable
solution. Designing a regulator that is cost-effective,
thermally sound, and efficient has become a challenge that
only multiphase converters can accomplish. The ISL6322G
controller helps simplify implementation by integrating vital
functions and requiring minimal external components. The
“Block Diagram” on page 3 provides a top level view of
multiphase power conversion using the ISL6322G controller.
I_L1 + I_L2 + I_L3, 7A/DIV
I_L3, 7A/DIV
PWM3, 5V/DIV
I_L2, 7A/DIV
I_L1, 7A/DIV
PWM2, 5V/DIV
PWM1, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Interleaving
The switching of each channel in a multiphase converter is
timed to be symmetrically out of phase with each of the other
channels. For example, in a 3-phase converter, each
channel switches 1/3 cycle after the previous channel and
1/3 cycle before the following channel. As a result, the
3-phase converter has a combined ripple frequency 3x
greater than the ripple frequency of any one phase. In
addition, the peak-to-peak amplitude of the combined
inductor currents is reduced in proportion to the number of
phases (Equations 1 and 2). Increased ripple frequency and
lower ripple amplitude mean that the designer can use less
per-channel inductance and lower total output capacitance
for any performance specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (I_L1, I_L2, and I_L3)
combine to form the AC ripple current and the DC load
current. The ripple component has 3x the ripple frequency of
each individual channel-current. Each PWM pulse is
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FN6715.0
May 22, 2008