ISL6322G Datasheet, PDF (12/39 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers, I2C Interface and Phase Dropping

ISL6322G
Phase Dropping
The ISL6322G has the ability to change the number of active
phases firing on-the-fly. This can be done through one of two
ways; through the use of the EN_PH2 pin, and through the
I²C interface.
The EN_PH2 pin is a digital logic input pin. Tieing this pin
high commands the part to operate in single phase mode
only. If EN_PH2 is tied low the part can operate in either
single phase or 2-phase mode depending on the state of
Bit 6 of I²C register 2. When the controller first powers up
Bit 6 is preset to “0”, which commands the controller to
operate in 2-phase mode. Changing bit 6 to a “1” commands
the controller to operate in single phase mode. For details on
how to change the state of the I²C registers please refer to
the “I²C Bus Interface” on page 26. If EN_PH2 is tied high,
the controller will operate in single phase mode only and will
ignore the state of Bit 6 in register 2, not allowing the I²C
interface to control the number of channel’s firing.
Once the ISL6322G receives a signal to change the number
of active phases it immediately responds by dropping or
adding phase 2 with no delay. When dropping from 2-phase
to single phase mode both LGATE2 and UGATE2 are
immediately tied low. These signals will stay in this state until
the controller is commanded to run in 2-phase mode again.
At this point LGATE2 and UGATE2 will be released to fire
normally.
Channel-Current Balance
One important benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multiphase converter be controlled to
carry equal amounts of current at any load level. To achieve
this, the currents through each channel must be sampled
every switching cycle. The sampled currents, I_n, from each
active channel are summed together and divided by the
number of active channels. The resulting cycle average
current, I_AVG, provides a measure of the total load-current
demand on the converter during each switching cycle.
Channel-current balance is achieved by comparing the
sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented
current-balance method is illustrated in Figure 3, with error
correction for Channel 1 represented. In the figure, the cycle
average current, I_AVG, is compared with the Channel 1
sample, I₁, to create an error signal I_ER.
The filtered error signal modifies the pulse width
commanded by V_COMP to correct any unbalance and force
I_ER toward zero. The same method for error signal
correction is applied to each active channel
.
V_COMP
+
-
FILTER f(s)
MODULATOR
RAMP
WAVEFORM
PWM1
+
-
TO GATE
CONTROL
LOGIC
I_ER
I_AVG
-
÷N
+
Σ
I_SEN2
I_SEN1
FIGURE 3. CHANNEL-1 PWM FUNCTION AND
CURRENT-BALANCE ADJUSTMENT
Continuous Current Sampling
In order to realize proper current-balance, the currents in
each channel are sensed continuously every switching
cycle. During this time the current-sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
inductor current, I_L. This sensed current, I_SEN, is simply a
scaled version of the inductor current.
PWM
SWITCHING PERIOD
I_L
I_SEN
TIME
FIGURE 4. CONTINUOUS CURRENT SAMPLING
The ISL6322G supports inductor DCR current sensing to
continuously sense each channel’s current for
channel-current balance (see Figure 4). The internal
circuitry, shown in Figure 5 represents Channel N of an
N-Channel converter. This circuitry is repeated for each
channel in the converter, but may not be active depending
on how many channels are operating.
12
FN6715.0
May 22, 2008