ISL6323A Datasheet, PDF (26/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323A
1.6
1.4
1.2
1.
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_{BOOT_CAP} (V)
FIGURE 17. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6323A provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See “Layout Considerations” on
page 32 for thermal transfer improvement suggestions.
When designing the ISL6323A into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P_{Qg_TOT}, due to the gate charge of MOSFETs and the
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 28
and 29, respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
P _{Q g _Q1}
=
3_--
2
⋅
Q_G1
⋅
P
V
CC
⋅
F_S
W
⋅
N_Q
1
⋅
N_P
H
ASE
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ F_SW ⋅ N_Q2 ⋅ N_PHASE
(EQ. 28)
(EQ. 29)
I_DR
=
⎛
⎝
3_--
2
⋅
Q_G1
⋅
N
Q1
+
Q_G2
⋅
N_Q
⎞
2⎠
⋅ N_PHASE ⋅ F_SW + I_Q
In Equations 28 and 29, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power
loss; the gate charge (Q_G1 and Q_G2) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I_Q is the driver total
quiescent current with no load at both drive outputs; N_Q1
and N_Q2 are the number of upper and lower MOSFETs per
phase, respectively; N_PHASE is the number of active
phases. The I_Q*VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
PVCC
BOOT
D
R_HI1
R_LO1
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
C_DS
Q1
PHASE
FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
LGATE
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance (P_{DR_UP}), the lower drive path resistance
(P_{DR_UP}), and in the boot strap diode (P_BOOT). The rest of
the power will be dissipated by the external gate resistors
(R_G1 and R_G2) and the internal gate resistors (R_GI1 and
R_GI2) of the MOSFETs. Figures 18 and 19 show the typical
upper and lower gate drives turn-on transition path. The total
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FN6878.0