ISL6323A Datasheet, PDF (22/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323A
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high.
V_NB
400mV/DIV
V_CORE
400mV/DIV
EN
5V/DIV
TDA
TDB
VDDPWRGD
5V/DIV
100µs/DIV
FIGURE 13. SOFT-START WAVEFORMS
Pre-Biased Soft-Start
The ISL6323A also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level. Both CORE and NB output support start-up into a
pre-charged output.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
V_CORE
400mV/DIV
EN
5V/DIV
Fault Monitoring and Protection
The ISL6323A actively monitors both CORE and NB output
voltages and currents to detect fault conditions. Fault
monitors trigger protective measures to prevent damage to
either load. One common power good indicator is provided
for linking to external system monitors. The schematic in
Figure 15 outlines the interaction between the fault monitors
and the power good signal.
Power Good Signal
The power good pin (VDDPWRGD) is an open-drain logic
output that signals whether or not the ISL6323A is regulating
both NB and CORE output voltages within the proper levels,
and whether any fault conditions exist. This pin should be
tied to a +5V source through a resistor.
During shutdown and soft-start, VDDPWRGD pulls low and
releases high after a successful soft-start and both output
voltages are operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected on either output or when the controller is disabled
by a POR reset or EN. In the event of an overvoltage or
overcurrent condition, the controller latches off and PGOOD
will not return high. Pending a POR reset of the ISL6323A
and successful soft-start, the PGOOD will return high.
Overvoltage Protection
The ISL6323A constantly monitors the sensed output voltage
on the VSEN pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level and
exceeds the PGOOD OV limit actions are taken by the
ISL6323A to protect the microprocessor load.
At the inception of an overvoltage event, both on-board
lower gate pins are commanded low as are the active PWM
outputs to the external drivers, the PGOOD signal is driven
low, and the ISL6323A latches off normal PWM action. This
turns on the all of the lower MOSFETs and pulls the output
voltage below a level that might cause damage to the load.
The lower MOSFETs remain driven ON until VDIFF falls
below 400mV. The ISL6323A will continue to protect the load
in this fashion as long as the overvoltage condition recurs.
Once an overvoltage condition ends the ISL6323A latches
off, and must be reset by toggling POR, before a soft-start
can be re-initiated.
100µs/DIV
FIGURE 14. SOFT-START WAVEFORMS FOR ISL6323A-
BASED MULTIPHASE CONVERTER
22
FN6878.0