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ISL6323A Datasheet, PDF (14/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors
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ISL6323A
MOSFET
DRIVER
VIN
UGATE(n)
LGATE(n)
ISL6323A INTERNAL CIRCUIT
In
ILn
L
DCR
INDUCTOR
VL(s)
VC(s)
R1
C
R2
VOUT
COUT
SAMPLE
+
-
ISEN
VC(s)
RISEN
ISENn-
ISENn+
VCC
RSET
RSET
CSET
FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
.
------L-------
DCR
=
-R-----1----⋅---R-----2--
R1 + R2
⋅
C
(EQ. 8)
The capacitor voltage VC, is then replicated across the
effective internal sense resistor, RISEN. This develops a
current through RISEN which is proportional to the inductor
current. This current, ISEN, is continuously sensed and is
then used by the controller for load-line regulation,
channel-current balancing, and overcurrent detection and
limiting. Equation 9 shows that the proportion between the
channel current, IL, and the sensed current, ISEN, is driven
by the value of the effective sense resistance, RISEN, and
the DCR of the inductor.
ISEN
=
IL ⋅
---D----C-----R-----
RISEN
(EQ. 9)
The effective internal RISEN resistance is important to the
current sensing process because it sets the gain of the load
line regulation loop when droop is enabled as well as the
gain of the channel-current balance loop and the overcurrent
trip level. The effective internal RISEN resistance is user
programmable and is set through use of the RSET pin.
Placing a single resistor, RSET, from the RSET pin to the
VCC pin programs the effective internal RISEN resistance
according to Equation 10.
RISEN
=
----3-----
400
⋅
RSET
(EQ. 10)
The North Bridge regulator samples the load current in the
same manner as the Core regulator does. The RSET resistor
will program all the effective internal RISEN resistors to the
same value.
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, In,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, IAVG, provides a measure of the total
load-current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented
current-balance method is illustrated in Figure 6, with error
correction for Channel 1 represented. In the figure, the cycle
average current, IAVG, is compared with the Channel 1
sample, I1, to create an error signal IER. The filtered error
signal modifies the pulse width commanded by VCOMP to
correct any unbalance and force IER toward zero. The same
method for error signal correction is applied to each active
channel.
VCOMP
+
-
FILTER f(s)
MODULATOR
RAMP
WAVEFORM
PWM1
+
-
TO GATE
CONTROL
LOGIC
IER
IAVG
-
÷N
+
I4
Σ
I3
I2
I1
NOTE: Channel 3 and 4 are optional.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
VID Interface
The ISL6323A supports hybrid power control of AMD
processors which operate from either a 6-bit parallel VID
interface (PVI) or a serial VID interface (SVI). The VID1/SEL pin
is used to command the ISL6323A into either the PVI mode or
the SVI mode. Whenever the EN pin is held LOW, both the
14
FN6878.0
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