ISL6323A Datasheet, PDF (25/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323A
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(r_DS(ON)). In Equation 21, I_M is the maximum continuous
output current, I_P-P is the peak-to-peak inductor current and
d is the duty cycle (V_OUT/V_IN).
P_{LOW, 1}
= r_DS(ON) ⋅
⎛
⎜
⎝
I--_{M---⎟⎞}
N⎠
2
⋅
(
1
–
d
)
+
I--_{L----(--P------P----)}²_---⋅_---(_---1----–_-----d----)
12
(EQ. 21)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I_M, V_D(ON), the switching
frequency, f_S, and the length of dead times, t_d1 and t_d2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
PLOW_{, 2}
=
VD_(ON) ⋅ fS ⋅
⎜⎛^I--M---- ₊ ^{I--P-------P---}⎟⎞ ⋅
⎝N 2 ⎠
td1
+
⎛
⎜
⎜
⎝
I--M----
N
–
I--P---2----P---_{⎠⎟⎟⎞}
⋅
td2
(EQ. 22)
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P_LOW,1 and P_LOW,2.
UPPER MOSFET POWER CALCULATION
In addition to r_DS(ON) losses, a large portion of the
upper-MOSFET losses are due to currents conducted
across the input voltage (V_IN) during switching. Since a
substantially higher portion of the upper-MOSFET losses are
dependent on switching frequency, the power calculation is
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode
reverse-recovery charge, Q_rr, and the upper MOSFET
r_DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 23,
the required time for this commutation is t₁ and the
approximated associated power loss is P_UP,1.
P _{U P,1}
≈
V_IN
⋅
⎛
⎝
I--_M---
N
+
I--_{P--2-----P--⎠⎞}
⋅
⎛
⎜
t--_1--
⎞
⎟
⎝ ²âŽ 
⋅
f_S
(EQ. 23)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t₂. In Equation 24, the
approximate power loss is P_UP,2.
P_{UP, 2}
≈
V_IN
⋅
⎛
⎜
I--_M---
⎝^N
–
I--_{P----P--⎟⎞}
2_⎠
⋅
⎛
⎜
⎝
t--_2--
⎞
⎟
2_⎠
⋅
f_S
(EQ. 24)
A third component involves the lower MOSFET reverse-
recovery charge, Q_rr. Since the inductor current has fully
commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q_rr, it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P_UP,3.
P_UP,3 = V_IN ⋅ Q_rr ⋅ f_S
(EQ. 25)
Finally, the resistive part of the upper MOSFET is given in
Equation 26 as P_UP,4.
P_UP,4 ≈ r_DS(ON) ⋅
⎛
⎜
I--_{M---⎟⎞}
2
⋅
d
+
I--_P----P--²_-
⎝ N⎠
12
(EQ. 26)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 23, 24, 25 and 26. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from Equation 27:
C_B
O
O
T
_CAP
≥
----------^Q-----^G----^A----^T---^E-----------
Δ V_{B O O T _CAP}
(EQ. 27)
Q_GATE=
Q_{-----G-----1----}•_-----P_----V_-----C_----C_---
V_GS1
•
N_Q1
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
control MOSFETs. The ΔV_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive.
25
FN6878.0