ISL6323A Datasheet, PDF (17/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323A
ISL6323A is designed to support the potential change of
state of these inputs. If VFIXEN is high, the IC decodes the
SVC and SVD states per Table 3.
Once enabled, the ISL6323A begins to soft-start both VDD
and VDDNB planes to the programmed VFIX level. The
internal soft-start circuitry slowly stair steps the reference up
to the target value and this results in a controlled ramp of the
power planes. Once soft-start has ended and both output
planes are within regulation limits, the VDDPWRGD pin
transitions high. If the EN input falls below the enable falling
threshold, then the controller ramps both VDD and VDDNB
down to near zero.
SVI MODE
Once the controller has successfully soft-started and
VDDPWRGD transitions high, the Northbridge SVI interface
can assert PWROK to signal the ISL6323A to prepare for
SVI commands. The controller actively monitors the SVI
interface for set VID commands to move the plane voltages
to start-up VID values. Details of the SVI Bus protocol are
provided in the AMD Design Guide for Voltage Regulator
Controllers Accepting Serial VID Codes specification.
Once the set VID command is received, the ISL6323A
decodes the information to determine which plane and the
VID target required (see Table 4). The internal DAC circuitry
steps the required output plane voltage to the new VID level.
During this time one or both of the planes could be targeted.
In the event the core voltage plane, VDD, is commanded to
power off by serial VID commands, the VDDPWRGD signal
remains asserted. The Northbridge voltage plane must
remain active during this time.
If the PWROK input is deasserted, then the controller steps
both VDD and VDDNB planes back to the stored Pre-
PWROK metal VID level in the holding register from initial
soft-start. No attempt is made to read the SVC and SVD
inputs during this time. If PWROK is reasserted, then the
on-board SVI interface waits for a set VID command.
If VDDPWRGD deasserts during normal operation, both
voltage planes are powered down in a controlled fashion.
The internal DAC circuitry stair steps both outputs down to
near zero.
SVID[6:0]
000_0000b
000_0001b
000_0010b
000_0011b
000_0100b
000_0101b
000_0110b
000_0111b
000_1000b
000_1001b
000_1010b
000_1011b
000_1100b
000_1101b
000_1110b
000_1111b
001_0000b
001_0001b
001_0010b
001_0011b
001_0100b
001_0101b
001_0110b
001_0111b
001_1000b
001_1001b
VOLTAGE (V)
1.5500
1.5375
1.5250
1.5125
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
1.2750
1.2625
1.2500
1.2375
SVID[6:0]
010_0000b
010_0001b
010_0010b
010_0011b
010_0100b
010_0101b
010_0110b
010_0111b
010_1000b
010_1001b
010_1010b
010_1011b
010_1100b
010_1101b
010_1110b
010_1111b
011_0000b
011_0001b
011_0010b
011_0011b
011_0100b
011_0101b
011_0110b
011_0111b
011_1000b
011_1001b
TABLE 4. SERIAL VID CODES
VOLTAGE (V)
SVID[6:0]
1.1500
100_0000b
1.1375
100_0001b
1.1250
100_0010b
1.1125
100_0011b
1.1000
100_0100b
1.0875
100_0101b
1.0750
100_0110b
1.0625
100_0111b
1.0500
100_1000b
1.0375
100_1001b
1.0250
100_1010b
1.0125
100_1011b
1.0000
100_1100b
0.9875
100_1101b
0.9750
100_1110b
0.9625
100_1111b
0.9500
101_0000b
0.9375
101_0001b
0.9250
101_0010b
0.9125
101_0011b
0.9000
101_0100b
0.8875
101_0101b
0.8750
101_0110b
0.8625
101_0111b
0.8500
101_1000b
0.8375
101_1001b
VOLTAGE (V)
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875*
0.4750*
0.4625*
0.4500*
0.4375*
SVID[6:0]
110_0000b
110_0001b
110_0010b
110_0011b
110_0100b
110_0101b
110_0110b
110_0111b
110_1000b
110_1001b
110_1010b
110_1011b
110_1100b
110_1101b
110_1110b
110_1111b
111_0000b
111_0001b
111_0010b
111_0011b
111_0100b
111_0101b
111_0110b
111_0111b
111_1000b
111_1001b
VOLTAGE (V)
0.3500*
0.3375*
0.3250*
0.3125*
0.3000*
0.2875*
0.2750*
0.2625*
0.2500*
0.2375*
0.2250*
0.2125*
0.2000*
0.1875*
0.1750*
0.1625*
0.1500*
0.1375*
0.1250*
0.1125*
0.1000*
0.0875*
0.0750*
0.0625*
0.0500*
0.0375*
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