ISL6323A Datasheet, PDF (18/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323A
TABLE 4. SERIAL VID CODES (Continued)
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
001_1010b
1.2250
011_1010b
0.8250
101_1010b
0.4250*
001_1011b
1.2125
011_1011b
0.8125
101_1011b
0.4125*
001_1100b
1.2000
011_1100b
0.8000
101_1100b
0.4000*
001_1101b
1.1875
011_1101b
0.7875
101_1101b
0.3875*
001_1110b
1.1750
011_1110b
0.7750
101_1110b
0.3750*
001_1111b
1.1625
011_1111b
0.7625
101_1111b
0.3625*
NOTE: *Indicates a VID not required for AMD Family 10h processors.
SVID[6:0]
111_1010b
111_1011b
111_1100b
111_1101b
111_1110b
111_1111b
VOLTAGE (V)
0.0250*
0.0125*
OFF
OFF
OFF
OFF
POWER SAVINGS MODE: PSI_L
Bit 7 of the Serial VID codes transmitted as part of the 8-bit
data phase over the SVI bus is allocated for the PSI_L. If
Bit 7 is 0, then the processor is at an optimal load for the
regulator to enter power savings mode. If Bit 7 is 1, then the
regulator should not be in power savings mode.
With the ISL6323A, Power Savings mode is realized through
phase shedding. Once a Serial VID command with Bit 7 set
to 0 is received, the ISL6323A will shed all phases in a
sequential manner until only Channel 1 is switching. If
active, Channel 4 will be shed first, followed by Channel 3
with Channel 2 being shed last. When a phase is shed, that
phase will not go into a tri-state mode until that phase would
have had its PWM go HIGH.
When leaving Power Savings Mode, through the reception of
a Serial VID command with Bit 7 set to 1, the ISL6323A will
sequentially turn on phases starting with Phase 2. When a
phase is being reactivated, it will not leave a tri-state until the
PWM of that phase goes HIGH.
If, while in Power Savings Mode, a Serial VID command is
received that forces a VID level change while maintaining
Bit 7 at 0, the ISL6323A will first exit the Power Savings
Mode state as previously described. The output voltage will
then be stepped up or down to the appropriate VID level.
Finally, the ISL6323A will then re-enter Power Savings
Mode.
Voltage Regulation
The integrating compensation network shown in Figure 8
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage and offset
errors in the OFS current source, remote-sense and error
amplifiers. Intersil specifies the guaranteed tolerance of the
ISL6323A to include the combined tolerances of each of
these elements.
The output of the error amplifier, V_COMP, is used by the
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 11. The internal and external
circuitry that controls voltage regulation is illustrated in
Figure 8.
.
V_OUT = V_REF – V_OFS – V_DROOP
(EQ. 11)
The ISL6323A incorporates differential remote-sense
amplification in the feedback path. The differential sensing
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output voltage.
EXTERNAL CIRCUIT
FS
R_FS
COMP
ISL6323A INTERNAL CIRCUIT
DROOP
CONTROL
TO
OSCILLATOR
C_C
R_C
FB
R_FB
+
(V_DROOP + V_OFS)
-
+
V_OUT
-
VSEN
RGND
8 I_AVG
I_OFS
-
V_COMP
+ _ERROR
AMPLIFIER
2k
∑
VID
DAC
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output
voltage can effectively be level shifted in a direction which
works to achieve a cost-effective solution can help to reduce
the output-voltage spike that results from fast load-current
demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
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