ISL6323A Datasheet, PDF (19/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323A
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied ground, a
current eight times the average current of all active
channels, 8*I_AVG, flows from FB through a load-line
regulation resistor R_FB. The resulting voltage drop across
R_FB is proportional to the output current, effectively creating
an output voltage droop with a steady-state value defined as
in Equation 12:
V_DROOP = I_AVG ⋅ R_FB
(EQ. 12)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
shown in Equation 13.
V_OUT
=
V_REF
–
V_O
F
S
–
⎛
⎜
⎝
-^I-^O-----^U----^T--
N
⋅
D
C
R
⋅
⎛
⎝
4_----0_---0_--
3
⋅
-_R----_S--¹--_E----_T- _⎠⎞
⋅K⋅
⎞
R _{F B⎠⎟}
(EQ. 13)
In Equation 13, V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_OUT is the total output current
of the converter, K_I is an internal gain determined by the
R_SET resistor connected to the RSET pin (K_I is defined in
Equation 10), K is the DC gain of the RC filter across the
inductor (K is defined in Equation 7), N is the number of
active channels, and DCR is the Inductor DCR value.
Output-Voltage Offset Programming
The ISL6323A allows the designer to accurately adjust the
offset voltage by connecting a resistor, R_OFS, from the OFS
pin to VCC or GND. When R_OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I_OFS) to flow into the FB pin
and out of the OFS pin. If R_OFS is connected to ground, the
voltage across it is regulated to 0.3V, and I_OFS flows into the
OFS pin and out of the FB pin. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product
(I_OFS x R_FB). These functions are shown in Figures 9 and
10.
Once the desired output offset voltage has been determined,
use the formulas in Equations 14 and 15 to set R_OFS:
For Positive Offset (connect R_OFS to GND):
R_OFS
=
-⁰---^.--³-----^×-----^R----^F----^B--
V_OFFSET
(EQ. 14)
For Negative Offset (connect R_OFS to VCC):
R_OFS
=
-¹---^.--⁶-----^×-----^R----^F----^B--
V_OFFSET
(EQ. 15)
VDIFF
-
V_{OFS RFB}
+
VREF
E/A
FB
I_OFS
VCC
R_OFS
OFS
ISL6323A
+
0.3V
-
-
1.6V
+
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
V_OUT
+
V_{OFS RFB}
-
VREF
E/A
FB
I_OFS
R_OFS
OFS
ISL6323A
GND
+
0.3V
-
-
1.6V
+
GND
VCC
FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6323A through
either the PVI or SVI interface. The ISL6323A manages the
resulting VID-on-the-Fly transition in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption. The ISL6323A begins slewing the
DAC at 3.25mV/µs until the DAC and target voltage are
19
FN6878.0