ISL6323A Datasheet, PDF (10/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323A
when the POR-trip point of the external driver is reached, the
voltage at this pin meets the above mentioned threshold level.
FS
A resistor, placed from FS to Ground or from FS to VCC,
sets the switching frequency of both controllers. Refer to
Equation 1 for proper resistor calculation.
R_T
=
[ 10.61
10
–
1.035 log
(fs
)]
(EQ. 1)
With the resistor tied from FS to Ground, Droop is enabled.
With the resistor tied from FS to VCC, Droop is disabled.
VSEN and RGND
VSEN and RGND are inputs to the core voltage regulator
(VR) controller precision differential remote-sense amplifier
and should be connected to the sense pins of the remote
processor core(s), VDDFB[H,L].
FB and COMP
These pins are the internal error amplifier inverting input and
output respectively of the core VR controller. FB, VSEN and
COMP are tied together through external R-C networks to
compensate the regulator.
APA
Adaptive Phase Alignment (APA) pin for setting trip level and
adjusting time constant. A 100µA current flows into the APA
pin and by tying a resistor from this pin to COMP the trip
level for the Adaptive Phase Alignment circuitry can be set.
OFS
The OFS pin provides a means to program a dc current for
generating an offset voltage across the resistor between FB
and VSEN The offset current is generated via an external
resistor and precision internal voltage references. The polarity
of the offset is selected by connecting the resistor to GND or
VCC. For no offset, the OFS pin should be left unconnected.
ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, ISEN3+,
ISEN4- and ISEN4+
These pins are used for differentially sensing the
corresponding channel output currents. The sensed currents
are used for channel balancing, protection, and core load
line regulation.
Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node
between the RC sense elements surrounding the inductor of
their respective channel. Tie the ISEN+ pins to the VCORE
side of their corresponding channel’s sense capacitor.
UGATE1 and UGATE2
Connect these pins to the corresponding upper MOSFET
gates. These pins are used to control the upper MOSFETs
and are monitored for shoot-through prevention purposes.
Maximum individual channel duty cycle is limited to 93.3%.
BOOT1 and BOOT2
These pins provide the bias voltage for the corresponding
upper MOSFET drives. Connect these pins to
appropriately-chosen external bootstrap capacitors. Internal
bootstrap diodes connected to the PVCC1_2 pin provide the
necessary bootstrap charge.
PHASE1 and PHASE2
Connect these pins to the sources of the corresponding
upper MOSFETs. These pins are the return path for the
upper MOSFET drives.
LGATE1 and LGATE2
These pins are used to control the lower MOSFETs. Connect
these pins to the corresponding lower MOSFETs’ gates.
PWM3 and PWM4
Pulse-width modulation outputs. Connect these pins to the
PWM input pins of an Intersil driver IC if 3- or 4-phase
operation is desired. Connect the ISEN- pins of the channels
not desired to +5V to disable them and configure the core
VR controller for 2- or 3-phase operation.
PWROK
System wide Power Good signal. If this pin is low, the two
SVI bits are decoded to determine the “metal VID”. When pin
is high, the SVI is actively running its protocol.
RSET
Connect this pin to VCC through a resistor to set the
effective value of the internal RISEN current sense resistors.
An external PTC thermistor network can also be used to
thermally compensate the current sense resistors to account
for changes in inductor DCR over-temperature.
VDDPWRGD
During normal operation this pin indicates whether both output
voltages are within specified overvoltage and undervoltage
limits. If either output voltage exceeds these limits or a reset
event occurs (such as an overcurrent event), the pin is pulled
low. This pin is always low prior to the end of soft-start.
RGND_NB
This pin is an input to the NB VR controller precision
differential remote-sense amplifier and should be connected
to the sense pin of the North Bridge, VDDNBFBL.
DVC
The DVC pin is a buffered version of the reference to the error
amplifier. A series resistor and capacitor between the DVC pin
and FB pin smooth the voltage transition during VID-on-the-fly
operations.
FB_NB and COMP_NB
These pins are the internal error amplifier inverting input and
output respectively of the NB VR controller. FB_NB,
VDIFF_NB, and COMP_NB are tied together through
external R-C networks to compensate the regulator.
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FN6878.0