ISL6323A Datasheet, PDF (23/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323A
100µA
I_NB
-
OCP
+
NB ONLY
-
OCL
+
142µA
I₁
REPEAT FOR EACH
CORE CHANNEL
-
OCP
+
100µA
I_AVG
CORE ONLY
SOFT-START, FAULT
AND CONTROL LOGIC
NB ONLY
1.8V
+
OVP
-
ISEN_NB+
DAC - 300mV
CORE ONLY
1.8V
DAC + 250mV
-
UV
+
+
OVP
-
-
OV
+
VDDPWRGD
VSEN
DAC - 300mV
-
UV
+
ISL6323A INTERNAL CIRCUITRY
FIGURE 15. POWER GOOD AND PROTECTION CIRCUITRY
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6323A is designed to protect either load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10kΩ resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
MOSFET should have a gate threshold well below the
maximum voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Undervoltage Detection
The undervoltage threshold is set at VDAC - 300mV typical.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above VDAC - 250mV typical.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6323A is designed to detect this
and shut down the controller. This event is detected by
monitoring small currents that are fed out the VSEN and
RGND pins. In the event of an open sense line fault, the
controller will continue to remain off until the fault goes away,
at which point the controller will re-initiate a soft-start
sequence.
Overcurrent Protection
The ISL6323A takes advantage of the proportionality
between the load current and the average current, I_AVG, to
detect an overcurrent condition. See “Continuous Current
Sampling” on page 13 and “Channel-Current Balance” on
page 14 for more detail on how the average current is
measured. Once the average current exceeds 100µA, a
comparator triggers the converter to begin overcurrent
protection procedures. The Core regulator and the North
Bridge regulator have the same type of overcurrent
protection.
The overcurrent trip threshold is dictated by the DCR of the
inductors, the number of active channels, the DC gain of the
inductor RC filter and the R_SET resistor. The overcurrent trip
threshold is shown in Equation 20.
I_OCP
=
100 μ A
⋅
-----^N--------
DCR
⋅
-¹--
K
⋅
⎛
⎝
----³-----
400
⋅
R_S
⎞
E T⎠
–
V_{-----I--N-----–----}N_------⋅_---V_{----O-----U----T--}
2 ⋅ L ⋅ f_S
⋅
-^V----^O----^U----^T--
V_IN
(EQ. 20)
Where:
K = -------^R-----²--------
R₁ + R₂
See “Continuous Current Sampling” on
page 13.
f_SW = Switching Frequency
Equation 20 is valid for both the Core regulator and the
North Bridge regulator. This equation includes the DC load
current as well as the total ripple current contributed by all
the phases. For the North Bridge regulator, N is 1.
During soft-start, the overcurrent trip point is boosted by a
factor of 1.4. Instead of comparing the average measured
current to 100µA, the average current is compared to 140µA.
Immediately after soft-start is over, the comparison level
changes to 100µA. This is done to allow for start-up into an
active load while still supplying output capacitor in-rush
current.
CORE REGULATOR OVERCURRENT
At the beginning of overcurrent shutdown, the controller sets
all of the UGATE and LGATE signals low, puts PWM3 and
PWM4 (if active) in a high-impedance state, and forces
VDDPWRGD low. This turns off all of the upper and lower
MOSFETs. The system remains in this state for fixed period
of 12ms. If the controller is still enabled at the end of this wait
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