80C187 Datasheet, PDF (8/30 Pages) Intel Corporation – 80-BIT MATH COPROCESSOR

80C187
The low-order byte of this control word configures
exception masking Bits 5–0 of the control word
contain individual masks for each of the six excep-
tions that the 80C187 recognizes
The high-order byte of the control word configures
the 80C187 operating mode including precision
rounding and infinity control
 The ‘‘infinity control bit’’ (bit 12) is not meaningful
to the 80C187 and programs must ignore its val-
ue To maintain compatibility with the 8087 this
bit can be programmed however regardless of
its value the 80C187 always treats infinity in the
affine sense (^{b % k a %}) This bit is initialized
to zero both after a hardware reset and after the
FINIT instruction
 The rounding control (RC) bits (bits 11–10) pro-
vide for directed rounding and true chop as well
as the unbiased round to nearest even mode
specified in the IEEE standard Rounding control
affects only those instructions that perform
rounding at the end of the operation (and thus
can generate a precision exception) namely
FST FSTP FIST all arithmetic instructions (ex-
cept FPREM FPREM1 FXTRACT FABS and
FCHS) and all transcendental instructions
 The precision control (PC) bits (bits 9–8) can be
used to set the 80C187 internal operating preci-
sion of the significand at less than the default of
64 bits (extended precision) This can be useful in
providing compatibility with early generation arith-
metic processors of smaller precision PC affects
only the instructions ADD SUB DIV MUL and
SQRT For all other instructions either the preci-
sion is determined by the opcode or extended
precision is used
Table 3 Condition Code Interpretation after FPREM and FPREM1 Instructions
Condition Code
C2
C3
C1
C0
Interpretation after
FPREM and FPREM1
1
X
X
X
Incomplete Reduction
Further Iteration Required
for Complete Reduction
Q1
Q0
Q2
Q MOD 8
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
1
0
1
1
1
0
1
1
1
1
0
1
Complete Reduction
2
C0 C3 C1 Contain Three Least
3
Significant Bits of Quotient
4
5
6
7
Table 4 Condition Code Resulting from Comparison
Order
C3
C2
C0
TOP ^l Operand
0
0
0
TOP ^k Operand
0
0
1
TOP ^e Operand
1
0
0
Unordered
1
1
1
8