80C187 Datasheet, PDF (23/30 Pages) Intel Corporation – 80-BIT MATH COPROCESSOR

80C187
Timing Responses
All timings are measured at 1 5V unless otherwise specified
Symbol
T_rhqz (t27)
T_rlqv (t28)
T_ilbh (t29)
T_wlbv (t30)
T_klml (t31)
T_rhqh (t32)
T_rlbh (t33)
Parameter
NPRD Inactive to Data Float
NPRD Active to Data Valid
ERROR Active to Busy Inactive
NPWR Active to Busy Active
NPRD or NPWR Active
to PEREQ Inactive
Data Hold from NPRD Inactive
RESET Inactive to BUSY Inactive
12 5 MHz
Min Max
(ns) (ns)
18
50
104
80
80
2
80
16 MHz
Min Max
(ns) (ns)
18
45
104
60
60
2
60
NOTES
The data float delay is not tested
2 The float condition occurs when the measured output current is less than I_OL on D₁₅ – D₀
3 D₁₅ – D₀ loading C_L e 100 pF
4 BUSY loading C_L e 100 pF
5 On last data transfer of numeric instruction
Test
Conditions
Note 2
Note 3
Note 4
Note 4
Note 5
Note 3
Clock Timings
Symbol
T_clcl (t1a)
(t1B)
T_clch (t2a)
(t2b)
T_chcl (t3a)
(t3b)
T_ch2ch1(t4)
T_ch1ch2(t5)
Parameter
CLK Period
CLK Low Time
CLK High Time
CKM ^e 1
CKM ^e 0
CKM ^e 1
CKM ^e 0
CKM ^e 1
CKM ^e 0
12 5 MHz
Min Max
(ns) (ns)
80
250
40
125
35
9
35
13
10
10
NOTES
16 MHz operation is available only in divide-by-2 mode (CKM strapped LOW)
6 At 1 5V
7 At 0 8V
8 At 2 0V
9 CKM e 1 3 7V to 0 8V at 16 MHz 3 5V to 1 0V at 12 5 MHz
10 CKM e 1 0 8V to 3 7V at 16 MHz 1 0V to 3 5V at 12 5 MHz
16 MHz
Min Max
(ns) (ns)
NA NA
31 25 125
NA
7
NA
9
8
8
Test
Conditions
Note 6
Note 6
Note 6
Note 7
Note 6
Note 8
Note 9
Note 10
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