80C187 Datasheet, PDF (29/30 Pages) Intel Corporation – 80-BIT MATH COPROCESSOR

80C187
Instruction
80C187 Extensions to the 80C186 Instruction Set (Continued)
Byte
0
Encoding
Byte
1
Optional
Bytes 2 – 3
32-Bit
Real
Clock Count Range
32-Bit
Integer
64-Bit
Real
16-Bit
Integer
CONSTANTS (Continued)
FLDL2E e Load log₂(e) into ST(0)
ESC 001
1110 1010
42
FLDLG2 e Load log₁₀(2) into ST(0)
ESC 001
1110 1100
43
FLDLN2 e Load log_e(2) into ST(0)
ESC 001
1110 1101
43
ARITHMETIC
FADD e Add
Integer real memory with ST(0)
ST(i) and ST(0)
FSUB e Subtract
Integer real memory with ST(0)
ST(i) and ST(0)
FMUL e Multiply
Integer real memory with ST(0)
ST(i) and ST(0)
FDIV e Divide
Integer real memory with ST(0)
ST(i) and ST(0)
FSQRTⁱ e Square root
FSCALE e Scale ST(0) by ST(1)
FPREM e Partial remainder of
ST(0) d ST(1)
FPREM1 e Partial remainder
(IEEE)
FRNDINT e Round ST(0)
to integer
FXTRACT e Extract components
of ST(0)
FABS e Absolute value of ST(0)
FCHS e Change sign of ST(0)
ESC MF 0
ESC d P 0
MOD 000 R M
11000 ST(i)
ESC MF 0
ESC d P 0
MOD 10 R R M
1110 R R M
ESC MF 0
ESC d P 0
MOD 001 R M
1100 1 R M
ESC MF 0
ESC d P 0
ESC 001
ESC 001
MOD 11 R R M
1111 R R M
1111 1010
1111 1101
ESC 001
1111 1000
ESC 001
1111 0101
ESC 001
1111 1100
ESC 001
ESC 001
ESC 001
1111 0100
1110 0001
1110 0000
DISP
DISP
DISP
DISP
44 – 52
77 – 92 65 – 73
25 – 33^b
77 – 91
44 – 52
77 – 92 65 – 73
28 – 36^d
77 – 91^c
47 – 57
81 – 102 68 – 93
31 – 59^e
82 – 93
108 140 – 147^f 128 142 – 146^g
90^h
124 – 131
69 – 88
76 – 157
97 – 187
68 – 82
72 – 78
24
26 – 27
Shaded areas indicate instructions not available in 8087
NOTES
b Add 3 clocks to the range when d e 1
c Add 1 clock to each range when R e 1
d Add 3 clocks to the range when d e 0
e typical e 54 (When d e 0 48 – 56 typical e 51)
f Add 1 clock to the range when R e 1
g 153 – 159 when R e 1
h Add 3 clocks to the range when d e 1
i b0 ^s ST(0) ^s a %
29