80C187 Datasheet, PDF (15/30 Pages) Intel Corporation – 80-BIT MATH COPROCESSOR

80C187
Pin Name
BUSY
CKM
CLK
CMD0
CMD1
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
D₈
D₉
D₁₀
D₁₁
D₁₂
D₁₃
D₁₄
D₁₅
ERROR
No Connect
NPRD
NPS1
NPS2
NPWR
PEREQ
RESET
V_CC
V_SS
Table 8 PLCC Pin Cross-Reference
CERDIP Package
25
39
32
29
31
23
22
21
20
19
18
17
16
15
14
12
11
8
7
6
5
26
2
27
34
33
28
24
35
3 9 13 37 40
1 4 10 30 36 38
PLCC Package
28
44
36
32
35
26
25
24
22
21
20
19
18
17
16
14
13
9
8
7
5
29
6 11 23 33 40
30
38
37
31
27
39
1 3 10 15 42
2 4 12 34 41 43
System Reset (RESET)
A LOW to HIGH transition on this pin causes the
80C187 to terminate its present activity and to enter
a dormant state RESET must remain active (HIGH)
for at least four internal clock periods (The relation
of the internal clock period to CLK depends on
CLKM the internal clock may be different from that
of the CPU ) Note that the 80C187 is active internal-
ly for 25 clock periods after the termination of the
RESET signal (the HIGH to LOW transition of RE-
SET) therefore the first instruction should not be
written to the 80C187 until 25 internal clocks after
the falling edge of RESET Table 9 shows the status
of the output pins during the reset sequence After a
reset all output pins return to their inactive states
Table 9 Output Pin Status during Reset
Output
Pin Name
Value
during Reset
BUSY
HIGH
ERROR
HIGH
PEREQ
LOW
D₁₅ – D₀
TRI-STATE OFF
Processor Extension Request (PEREQ)
When active this pin signals to the CPU that the
80C187 is ready for data transfer to from its data
FIFO When there are more than five data transfers
15