80C187 Datasheet, PDF (26/30 Pages) Intel Corporation – 80-BIT MATH COPROCESSOR

80C187
CLK NPRD NPWR TIMING (CKM ^e 1)
CLK RESET TIMING (CKM ^e 0)
270640 – 16
RESET must meet timing shown to guarantee known phase of internal divide by 2 circuits
270640 – 17
NOTE
RESET NPWR NPRD inputs are asynchronous to CLK Timing requirements are given for testing purposes only to assure
recognition at a specific CLK edge
CLK NPRD NPWR TIMING (CKM ^e 0)
RESET BUSY TIMING
26
270640 – 18
270640 – 19