80C187 Datasheet, PDF (5/30 Pages) Intel Corporation – 80-BIT MATH COPROCESSOR

80C187
The 80C187 register set can be accessed either as
a stack with instructions operating on the top one or
two stack elements or as individually addressable
registers The TOP field in the status word identifies
the current top-of-stack register A ‘‘push’’ operation
decrements TOP by one and loads a value into the
new top register A ‘‘pop’’ operation stores the value
from the current top register and then increments
TOP by one The 80C187 register stack grows
‘‘down’’ toward lower-addressed registers
Instructions may address the data registers either
implicitly or explicitly Many instructions operate on
the register at the TOP of the stack These instruc-
tions implicitly address the register at which TOP
points Other instructions allow the programmer to
explicitly specify which register to use This explicit
addressing is also relative to TOP
TAG WORD
The tag word marks the content of each numeric
data register as Figure 3 shows Each two-bit tag
represents one of the eight data registers The prin-
cipal function of the tag word is to optimize the
NPX’s performance and stack handling by making it
possible to distinguish between empty and nonemp-
ty register locations It also enables exception han-
dlers to identify special values (e g NaNs or denor-
mals) in the contents of a stack location without the
need to perform complex decoding of the actual
data
STATUS WORD
The 16-bit status word (in the status register) shown
in Figure 4 reflects the overall state of the 80C187 It
may be read and inspected by programs
Bit 15 the B-bit (busy bit) is included for 8087 com-
patibility only It always has the same value as the
ES bit (bit 7 of the status word) it does not indicate
the status of the BUSY output of 80C187
Bits 13 – 11 (TOP) point to the 80C187 register that
is the current top-of-stack
The four numeric condition code bits (C₃ – C₀) are
similar to the flags in a CPU instructions that per-
form arithmetic operations update these bits to re-
flect the outcome The effects of these instructions
on the condition code are summarized in Tables 2
through 5
Bit 7 is the error summary (ES) status bit This bit is
set if any unmasked exception bit is set it is clear
otherwise If this bit is set the ERROR signal is as-
serted
Bit 6 is the stack flag (SF) This bit is used to distin-
guish invalid operations due to stack overflow or un-
derflow from other kinds of invalid operations When
SF is set bit 9 (C₁) distinguishes between stack
overflow (C₁ ^e 1) and underflow (C₁ ^e 0)
Figure 4 shows the six exception flags in bits 5 – 0 of
the status word Bits 5 – 0 are set to indicate that the
80C187 has detected an exception while executing
an instruction A later section entitled ‘‘Exception
Handling’’ explains how they are set and used
Note that when a new value is loaded into the status
word by the FLDENV or FRSTOR instruction the
value of ES (bit 7) and its reflection in the B-bit (bit
15) are not derived from the values loaded from
memory but rather are dependent upon the values of
the exception flags (bits 5 – 0) in the status word and
their corresponding masks in the control word If ES
is set in such a case the ERROR output of the
80C187 is activated immediately
15
TAG (7)
TAG (6)
TAG (5)
TAG (4)
TAG (3)
TAG (2)
TAG (1)
0
TAG (0)
NOTE
The index i of tag(i) is not top-relative A program typically uses the ‘‘top’’ field of Status Word to determine
which tag(i) field refers to logical top of stack
TAG VALUES
00 e Valid
01 e Zero
10 e QNaN SNaN Infinity Denormal and Unsupported Formats
11 e Empty
Figure 3 Tag Word
5