80C187 Datasheet, PDF (12/30 Pages) Intel Corporation – 80-BIT MATH COPROCESSOR

80C187
80C186 automatically tests the BUSY line from the
80C187 Numeric Processor Extension to ensure that
the 80C187 Numeric Processor Extension has com-
pleted its previous instruction before executing the
next ESC instruction No explicit WAIT instructions
are required to assure this synchronization For the
8087 used with 8086 and 8088 CPUs explicit WAITs
are required before each numeric instruction to en-
sure synchronization Although 8086 8087 pro-
grams having explicit WAIT instructions will execute
on the 80C186 80C187 these WAIT instructions
are unnecessary
The 80C187 supports only affine closure for infinity
arithmetic not projective closure
Operands for FSCALE and FPATAN are no longer
restricted in range (except for g ^%) F2XM1 and
FPTAN accept a wider range of operands
Rounding control is in effect for FLD constant
Software cannot change entries of the tag word to
values (other than empty) that differ from actual reg-
ister contents
After reset FINIT and incomplete FPREM the
80C187 resets to zero the condition code bits C₃ –
C₀ of the status word
In conformance with the IEEE standard the 80C187
does not support the special data formats
pseudozero pseudo-NaN pseudoinfinity and un-
normal
The denormal exception has a different purpose on
the 80C187 A system that uses the denormal-ex-
ception handler solely to normalize the denormal op-
erands would better mask the denormal exception
on the 80C187 The 80C187 automatically normal-
izes denormal operands when the denormal excep-
tion is masked
EXCEPTIONS
A number of differences exist due to changes in the
IEEE standard and to functional improvements to
the architecture of the 80C186 80C187
1 The 80C186 80C187 traps exceptions only on
the next ESC instruction i e the 80C186 does not
notice unmasked 80C187 exceptions on the
80C186 ERROR input line until a later numerics
instruction is executed Because the 80C186
does not sample ERROR on WAIT and FWAIT
instructions programmers should place an FNOP
instruction at the end of a sequence of numerics
instructions to force the 80C186 to sample its
ERROR input
2 The 80C187 Numeric Processor Extension sig-
nals exceptions through a dedicated ERROR line
to the CPU The 80C187 error signal does not
pass through an interrupt controller (the 8087 INT
signal does) Therefore any interrupt-controller-
oriented instructions in numerics exception han-
dlers for the 8086 8087 should be deleted
3 Interrupt vector 16 must point to the numerics ex-
ception handling routine
4 The ESC instruction address saved in the 80C187
Numeric Processor Extension includes any lead-
ing prefixes before the ESC opcode The corre-
sponding address saved in the 8087 does not
include leading prefixes
5 When the overflow or underflow exception is
masked the 80C187 differs from the 8087 in
rounding when overflow or underflow occurs The
80C187 produces results that are consistent with
the rounding mode
6 When the underflow exception is masked the
80C187 sets its underflow flag only if there is also
a loss of accuracy during denormalization
7 Fewer invalid-operation exceptions due to denor-
mal operands because the instructions FSQRT
FDIV FPREM and conversions to BCD or to inte-
ger normalize denormal operands before pro-
ceeding
8 The FSQRT FBSTP and FPREM instructions
may cause underflow because they support de-
normal operands
9 The denormal exception can occur during the
transcendental instructions and the FXTRACT in-
struction
10 The denormal exception no longer takes prece-
dence over all other exceptions
11 When the denormal exception is masked the
80C187 automatically normalizes denormal op-
erands The 8087 performs unnormal arithmetic
which might produce an unnormal result
12 When the operand is zero the FXTRACT in-
struction reports a zero-divide exception and
leaves ^{b %} in ST(1)
13 The status word has a new bit (SF) that signals
when invalid-operation exceptions are due to
stack underflow or overflow
14 FLD extended precision no longer reports denor-
mal exceptions because the instruction is not
numeric
15 FLD single double precision when the operand
is denormal converts the number to extended
precision and signals the denormalized oper-
12