80C187 Datasheet, PDF (16/30 Pages) Intel Corporation – 80-BIT MATH COPROCESSOR

80C187
PEREQ is deactivated after the first three transfers
and subsequently after every four transfers This sig-
nal always goes inactive before BUSY goes inactive
Busy Status (BUSY)
When active this pin signals to the CPU that the
80C187 is currently executing an instruction This
pin is active HIGH It should be connected to the
80C186’s TEST BUSY pin During the RESET se-
quence this pin is HIGH The 80C186 uses this
HIGH state to detect the presence of an 80C187
Error Status (ERROR)
This pin reflects the ES bit of the status register
When active it indicates that an unmasked excep-
tion has occurred This signal can be changed to
inactive state only by the following instructions (with-
out a preceding WAIT) FNINIT FNCLEX
FNSTENV FNSAVE FLDCW FLDENV and
FRSTOR This pin should be connected to the
ERROR pin of the CPU ERROR can change state
only when BUSY is active
Data Pins (D₁₅ – D₀)
These bidirectional pins are used to transfer data
and opcodes between the CPU and 80C187 They
are normally connected directly to the correspond-
ing CPU data pins Other buffers drivers driving the
local data bus must be disabled when the CPU
reads from the NPX High state indicates a value of
one D₀ is the least significant data bit
Numeric Processor Write (NPWR)
A signal on this pin enables transfers of data from
the CPU to the NPX This input is valid only when
NPS1 and NPS2 are both active
Numeric Processor Read (NPRD)
A signal on this pin enables transfers of data from
the NPX to the CPU This input is valid only when
NPS1 and NPS2 are both active
Numeric Processor Selects (NPS1 and NPS2)
Concurrent assertion of these signals indicates that
the CPU is performing an escape instruction and en-
ables the 80C187 to execute that instruction No
data transfer involving the 80C187 occurs unless the
device is selected by these lines
Command Selects (CMD0 and CMD1)
These pins along with the select pins allow the CPU
to direct the operation of the 80C187
System Power (V_CC)
System power provides the ^a5V g10% DC supply
input All V_CC pins should be tied together on the
circuit board and local decoupling capacitors should
be used between V_CC and V_SS
System Ground (V_SS)
All V_SS pins should be tied together on the circuit
board and local decoupling capacitors should be
used between V_CC and V_SS
Processor Architecture
As shown by the block diagram (Figure 1) the
80C187 NPX is internally divided into three sections
the bus control logic (BCL) the data interface and
control unit and the floating-point unit (FPU) The
FPU (with the support of the control unit which con-
tains the sequencer and other support units) exe-
cutes all numerics instructions The data interface
and control unit is responsible for the data flow to
and from the FPU and the control registers for re-
ceiving the instructions decoding them and se-
quencing the microinstructions and for handling
some of the administrative instructions The BCL is
responsible for CPU bus tracking and interface
BUS CONTROL LOGIC
The BCL communicates solely with the CPU using
I O bus cycles The BCL appears to the CPU as a
special peripheral device It is special in two re-
spects the CPU initiates I O automatically when it
encounters ESC instructions and the CPU uses re-
served I O addresses to communicate with the BCL
The BCL does not communicate directly with memo-
ry The CPU performs all memory access transfer-
ring input operands from memory to the 80C187 and
transferring outputs from the 80C187 to memory A
dedicated communication protocol makes possible
high-speed transfer of opcodes and operands be-
tween the CPU and 80C187
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