80C187 Datasheet, PDF (28/30 Pages) Intel Corporation – 80-BIT MATH COPROCESSOR

80C187
Instruction
DATA TRANSFER
FLD e Load^a
Integer real memory to ST(0)
80C187 Extensions to the 80C186 Instruction Set
Byte
0
Encoding
Byte
1
Optional
Bytes 2 – 3
32-Bit
Real
ESC MF 1
MOD 000 R M
DISP
40
Long integer memory to ST(0)
ESC 111
MOD 101 R M
DISP
Extended real memory to ST(0)
ESC 011
MOD 101 R M
DISP
BCD memory to ST(0)
ESC 111
MOD 100 R M
DISP
ST(i) to ST(0)
ESC 001
11000 ST(i)
FST e Store
ST(0) to integer real memory
ESC MF 1
MOD 010 R M
DISP
58
ST(0) to ST(i)
FSTP e Store and Pop
ST(0) to integer real memory
ESC 101
11010 ST(i)
ESC MF 1
MOD 011 R M
DISP
58
ST(0) to long integer memory
ESC 111
MOD 111 R M
DISP
ST(0) to extended real
ESC 011
MOD 111 R M
DISP
ST(0) to BCD memory
ESC 111
MOD 110 R M
DISP
ST(0) to ST(i)
ESC 101
11001 ST (i)
FXCH e Exchange
ST(i) and ST(0)
ESC 001
11001 ST(i)
COMPARISON
FCOM e Compare
Integer real memory to ST(0)
ESC MF 0
MOD 010 R M
DISP
48
ST(i) to ST(0)
ESC 000
11010 ST(i)
FCOMP e Compare and pop
Integer real memory to ST
ESC MF 0
MOD 011 R M
DISP
48
ST(i) to ST(0)
ESC 000
11011 ST(i)
FCOMPP e Compare and pop twice
ST(1) to ST(0)
ESC 110
1101 1001
FTST e Test ST(0)
ESC 001
1110 0100
FUCOM e Unordered compare
ESC 101
11100 ST(i)
FUCOMP e Unordered compare
and pop
ESC 101
11101 ST(i)
FUCOMPP e Unordered compare
and pop twice
ESC 010
1110 1001
FXAM e Examine ST(0)
ESC 001
11100101
Clock Count Range
32-Bit 64-Bit
Integer Real
16-Bit
Integer
65 – 72
59
90 – 101
74
296 – 305
16
67 – 71
93 – 107
73
13
80 – 93
93 – 107
73
116 – 133
83
542 – 564
14
80 – 93
20
78 – 85
67
77 – 81
26
78 – 85
67
77 – 81
28
28
30
26
28
28
32-40
CONSTANTS
FLDZ e Load a0 0 into ST(0)
ESC 001
1110 1110
22
FLD1 e Load a1 0 into ST(0)
ESC 001
1110 1000
26
FLDPI e Load pi into ST(0)
ESC 001
1110 1011
42
FLDL2T e Load log₂(10) into ST(0)
ESC 001
1110 1001
42
Shaded areas indicate instructions not available in 8087
NOTE
a When loading single- or double-precision zero from memory add 5 clocks
28