80C196EA Datasheet, PDF (33/46 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

8xC196EA — AUTOMOTIVE
6.4 Deferred Bus Timing Mode
Deferred Bus Cycle Mode: This bus mode (enabled
by setting CCB1.5) reduces bus contention when
using the 8xC196EA in demultiplexed mode with
slow memories. As shown in Figure 8, a delay of 2t
occurs in the first bus cycle following a chip-select
output change and the first write cycle following a
read cycle.
CLKOUT
ALE
RD#
AD15:0
(read)
WR#
AD15:0
(write)
BHE#, INST
A20:0
CSx#
T_LHLH + 2t
T_RHLH + 2t
Data In
T_AVWL + 2t
T_WHLH + 2t
T_AVRL + 2t
T_AVDV+ 2t
Data In
Data Out
Data Out
Data Out
Address Out
Valid
Valid
Figure 8. Deferred Bus Mode Timing Diagram
A3246-02
ADVANCE INFORMATION
27