80C196EA Datasheet, PDF (14/46 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

8xC196EA — AUTOMOTIVE
Name
BHE#
BREQ#
CLKOUT
CRBUSY#
CRDCLK
CRIN
CROUT
Type
O
O
O
O
I
I
O
Table 4. Signal Descriptions (Sheet 2 of 8)
Description
Byte High Enable^†
During 16-bit bus cycles, this active-low output signal is asserted for word and
high-byte reads and writes to external memory. BHE# indicates that valid data
is being transferred over the upper half of the system data bus. Use BHE#, in
conjunction with AD0, to determine which memory byte is being transferred
over the system bus:
BHE# AD0 Byte(s) Accessed
0
0 both bytes
0
1 high byte only
1
0 low byte only
BHE# shares a package pin with P5.5 and WRH#.
† _{The chip configuration register 0 (CCR0) determines whether this pin func-}
tions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
WRH#.
Bus Request
This active-low output signal is asserted during a hold cycle when the bus con-
troller has a pending external memory cycle.
You must enable the bus-hold protocol before using this signal.
BREQ# shares a package pin with P5.4.
Clock Output
Output of the internal clock generator. The CLKOUT frequency can be pro-
grammed to one of five frequencies: the internal operating frequency (f) divided
by a factor of two, four, eight, or sixteen, or the same frequency as the oscillator
input (F_XTAL1). CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7
Code RAM Busy
This signal indicates that the serial debug unit (SDU) is not ready to conduct a
transaction.
Code RAM Clock
Provides the clock signal for the serial debug unit (SDU). The maximum clock
frequency equals the operating frequency (f) divided by two.
Code RAM Data Input
Serial input for test instructions and data into the serial debug unit (SDU). Data
is transferred in 8-bit bytes with the most-significant bit (MSB) first. Each bit is
sampled on the rising edge of CRDCLK.
Code RAM Data Output
Serial output for data from the serial debug unit (SDU). Data is transferred in
8-bit bytes with the most-significant bit (MSB) first. Each bit is valid on the rising
edge of CRDCLK.
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ADVANCE INFORMATION