80C196EA Datasheet, PDF (19/46 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

Name
SD1:0
T1CLK
T2CLK
T3CLK
T4CLK
T1RST
T2RST
T3RST
T4RST
TMODE#
8xC196EA — AUTOMOTIVE
Type
I/O
I
I
I
I
I
I
I
I
I
Table 4. Signal Descriptions (Sheet 7 of 8)
Description
Data Pins for SSIO0 and 1
These pins are the data I/O pins for SSIO0 and 1.
SD0 shares a package pin with P10.1, and SD1 shares a package pin with
P10.1.
Timer 1 External Clock
External clock for Timer 1.Timer 1 is programmable to increment or decement
on the rising edge, the falling edge, or both rising and falling edges of T1CLK.
T1CLK shares a package pin with P7.0 and EPA0.
Timer 2 External Clock
External clock for timer 2. Timer 2 is programmable to increment or decement
on the rising edge, the falling edge, or both rising and falling edges of T2CLK.
External clock for the serial I/O baud-rate generator input (program selectable).
T2CLK shares a package pin with P7.2 and EPA2.
Timer 3 External Clock
External clock for timer 3. Timer 3 is programmable to increment or decement
on the rising edge, the falling edge, or both rising and falling edges of T3CLK.
T3CLK shares a package pin with P7.4 and EPA4.
Timer 4 External Clock
External clock for timer 4. Timer 2 is programmable to increment or decement
on the rising edge, the falling edge, or both rising and falling edges of T4CLK.
T4CLK shares a package pin with P7.6 and EPA6.
Timer 1 External Reset
External reset for timer 1. Timer 1 is programmable to reset on the rising edge,
the falling edge, or both rising and falling edges of T1RST.
T1RST shares a package pin with P7.1 and EPA1.
Timer 2 External Reset
External reset for timer 2. Timer 2 is programmable to reset on the rising edge,
the falling edge, or both rising and falling edges of T2RST.
T2RST shares a package pin with P7.3 and EPA3.
Timer 3 External Reset
External reset for timer 3. Timer 3 is programmable to reset on the rising edge,
the falling edge, or both rising and falling edges of T3RST.
T3RST shares a package pin with P7.5 and EPA5.
Timer 4 External Reset
External reset for timer 4. Timer 4 is programmable to reset on the rising edge,
the falling edge, or both rising and falling edges of T4RST.
T4RST shares a package pin with P7.6 and EPA6.
Test-Mode Entry
If this pin is held low during reset, the device will enter a test mode. The value of
several other pins defines the actual test mode. All test modes, except
test-ROM execution, are reserved for Intel factory use. If you choose to config-
ure this signal as an input, always hold it high during reset and ensure that your
system meets the V_IH specification to prevent inadvertent entry into test mode.
TMODE# shares a package pin with P5.4 and BREQ#.
ADVANCE INFORMATION
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