80C196EA Datasheet, PDF (29/46 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

8xC196EA — AUTOMOTIVE
6.3 AC Characteristics — Demultiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 9. AC Characteristics, Demultiplexed Bus Mode (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
F_XTAL1
Frequency on XTAL1, PLL in 1x mode
Frequency on XTAL1, PLL in 2x mode
20
40
MHz (1,8)
10
20
MHz (8)
f
Operating frequency, f = F_XTAL1; PLL in 1x mode
Operating frequency, f = 2F_XTAL1; PLL in 2x mode
20
40
Mhz
t
Period, t = 1/f
25
50
ns
T_AVDV
T_RLDV
T_AVWL
T_AVRL
T_SLDV
T_CHDV
T_RHDZ
T_RHRL
T_RXDX
T_XHCH
T_CLCL
Address Valid to Input Data Valid
RD# Low to Input Data Valid
Address Valid to WR# Low
Address Valid to RD# Low
Chip Select Low to Data Valid
CLKOUT Rising Edge to Input Data Valid
RD# High to Input Data Float
Read High to Next Read Low
Data Hold after RD# Inactive
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
4t – 23 ns (2)
3t – 25 ns (2)
t
ns
t–8
ns
4t – 27 ns (2)
2t – 25 ns (9)
t-5
ns
t–5
ns
0
ns
10
35
ns (9)
2t
ns (9)
T_CHCL CLKOUT High Period
t – 10
t + 10
ns (9)
T_CLLH CLKOUT Falling ALE Rising
– 10
10
ns (9)
T_RLCL
RD# Low to CLKOUT Low
–5
5
ns (9)
T_RLRH RD# Low to RD# High
3t – 12
ns (2)
T_RHLH RD# Rising to ALE Rising
t–4
t + 12
ns (3)
T_WLCL WR# Low to CLKOUT Falling
– 12
5
ns (9)
T_QVWH Data Stable to WR# Rising Edge
3t – 18
ns (3)
NOTES:
1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz
can be applied with an external clock source.
2. If wait states are used, add 2t × n, where n = number of wait states.
3. Assuming back-to-back bus cycles.
4. When forcing wait states using the BUSCON register, add 2t × n.
5. Exceeding the maximum specification causes additional wait states.
6. 8-bit bus only.
7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed
wait state is required.
8. Device is static by design but has been tested only down to 20 MHz.
9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
ADVANCE INFORMATION
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