80C196EA Datasheet, PDF (20/46 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

8xC196EA — AUTOMOTIVE
Name
TXD1:0
V_CC
V_REF
V_SS
WR#
WRH#
WRL#
XTAL1
XTAL2
Type
O
PWR
PWR
GND
O
O
O
I
O
Table 4. Signal Descriptions (Sheet 8 of 8)
Description
Transmit Serial Data 0 and 1
In serial I/O modes 1, 2, and 3, TXD0 and 1 transmit serial port output data. In
mode 0, they are the serial clock output.
TXD0 shares a package pin with P2.0 and TXD1 shares a package pin with
P2.3.
Digital Supply Voltage
Connect each V_CC pin to the digital supply voltage.
Reference Voltage for the A/D Converter
This pin also supplies operating voltage to the analog portion of the A/D con-
verter.
Digital Circuit Ground
These pins supply ground for the digital circuitry. Connect each V_SS pin to
ground through the lowest possible impedance path.
Write^†
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
WR# is multiplexed with P5.2 and WRL#.
† _{The chip configuration register 0 (CCR0) determines whether this pin func-}
tions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
Write High^†
During 16-bit bus cycles, this active-low output signal is asserted for high-byte
writes and word writes to external memory. During 8-bit bus cycles, WRH# is
asserted for all write operations.
WRH# shares a package pin with P5.5 and BHE#.
† _{The chip configuration register 0 (CCR0) determines whether this pin func-}
tions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
WRH#.
Write Low^†
During 16-bit bus cycles, this active-low output signal is asserted for low-byte
writes and word writes to external memory. During 8-bit bus cycles, WRL# is
asserted for all write operations.
WRL# shares a package pin with P5.2 and WR#.
† _{The chip configuration register 0 (CCR0) determines whether this pin func-}
tions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator and the internal clock generators. The internal
clock generators provide the peripheral clocks, CPU clock, and CLKOUT sig-
nal. When using an external clock source instead of the on-chip oscillator, con-
nect the clock input to XTAL1. The external clock signal must meet the V_IH
specification for XTAL1.
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design
uses an external clock source instead of the on-chip oscillator.
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ADVANCE INFORMATION