80C196EA Datasheet, PDF (16/46 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

8xC196EA — AUTOMOTIVE
Name
INST
NMI
ONCE#
OS7:0
P2.7:0
P3.7:0
P4.7:0
Type
O
I
I
O
I/O
I/O
I/O
Table 4. Signal Descriptions (Sheet 4 of 8)
Description
Instruction Fetch
This active-high output signal is valid only during external memory bus cycles.
When high, INST indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle of an external
instruction fetch. INST is low for data accesses, including interrupt vector
fetches and chip configuration byte reads. INST is low during internal memory
fetches.
INST shares a package pin with P5.1.
Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a nonmaskable
interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for
greater than one state time to guarantee that it is recognized.
On-circuit Emulation
Holding ONCE# low during the rising edge of RESET# places the device into
on-circuit emulation (ONCE) mode. PLLEN must also be held low. This mode
puts all pins into a high-impedance state, thereby isolating the device from
other components in the system. The value of ONCE# is latched when the
RESET# pin goes inactive. While the device is in ONCE mode, you can debug
the system using a clip-on emulator.
To exit ONCE mode, reset the device by pulling the RESET# signal low. To pre-
vent inadvertent entry into ONCE mode, either configure this pin as an output or
hold it high during reset and ensure that your system meets the V_IH specifica-
tion.
ONCE# shares a package pin with P2.6.
Event Processor Array (EPA) Compare-only Channels with Simulcapture
Outputs of the EPA’s compare-only channels. These pins are multiplexed with
port 9 and may be configured as standard I/O.
OS7:0 share package pins with P9.7:0.
Port 2
This is a standard, 8-bit, bidirectional port that is multiplexed with individually
selectable special-function signals. P2.6 is multiplexed with ONCE#. To prevent
inadvertent entry into ONCE mode, either configure this pin as an output or hold
it high during reset and ensure that your system meets the V_IH specification.
Port 2 shares package pins with the following signals: P2.0/TXD0, P2.1/RXD0,
P2.2/EXTINT, P2.3/TXD1, P2.4/RXD1, P2.6/ONCE#, and P2.7/CLKOUT.
Port 3
This is a memory-mapped, 8-bit, bidirectional port with programmable
open-drain or complementary output modes. The pins are shared with the mul-
tiplexed address/data bus, which has complementary drivers.
P3.7:0 share package pins with AD7:0.
Port 4
This is a memory-mapped, 8-bit, bidirectional port with programmable
open-drain or complementary output modes. The pins are shared with the mul-
tiplexed address/data bus, which has complementary drivers.
P4.7:0 share package pins with AD15:8.
10
ADVANCE INFORMATION